U.S. Court of Appeals for the Federal Circuit Live Stream Courtroom 402

4:56Good morning and welcome to the United

4:59States Court of Appeals for the Federal

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17:02All right.

17:08United States Court of Appeals Federal

17:10Circuit

17:18Be seated, please.

17:20>> We have four argued cases this morning.

17:22The first is number 242304

17:26Net List Inc. versus Samsung

17:28Electronics. Mr. Lamin,

17:32just before you begin to be clear about

17:34this, Samsung is now out of these cases,

17:37right? Because of the global settlement.

17:39>> That is correct, your honor.

17:40>> So, they should be removed from the

17:41caption.

17:42>> Pardon? It should be removed from the

17:44caption then.

17:45>> That's correct. They're no longer

17:46participating. So, it's back to

17:48>> Thank you. May it please the court. I'd

17:50like to focus on two issues. Um, while I

17:53would like to start with claim scope, I

17:55also want to be sure to address the

17:56PTAB's written description

17:57determination, especially for the 436

18:00patent where the PTAB relied on its own

18:03internet research outside the record

18:05from nearly 20 years outside the

18:07relevant date. But beginning with claim

18:09construction, the claim itself and the

18:11extrinsic ev intrinsic evidence all

18:13indicate that the recited ranks are have

18:16more than one memory device. And if you

18:18turn to the last limitation on the

18:20inside front cover of our brief, it's

18:22limitation E labeled there. It says

18:25wherein a command signal is transmitted

18:27to only one DDR memory device at a time.

18:32Words only one and at a time are

18:34inconsistent with a rank having only one

18:36device. If I said, "I will only speak to

18:40only one student at a time," one would

18:42not think I was talking about a class

18:44that has only one student. Same thing

18:46here. Those words make it clear that

18:48we're looking at uh ranks that have

18:50multiple devices. In fact, the invention

18:52is actually akin to

18:53>> Does that does that clause refer to a

18:56rank or does it refer to the module in

18:59general? I think it refers to the ranks

19:02because if you look up a little bit

19:03higher, it talks about um saying that

19:06it's going to single out and transmit to

19:08only um to select one one rank or two.

19:11And I think all the parties understood

19:13when they're looking at it, they were

19:14talking about within a rank. The debate

19:15was does it encompass single device

19:18ranks or is it multiple device ranks?

19:20And that's that was the understanding.

19:22And even if you were to look at it that

19:23way, I don't think that would solve the

19:25problem because since it talks about

19:27selecting one rank or two ranks, if I

19:29said I'm going to select one or two

19:31classrooms and I will speak to only one

19:34student at a time, you're still not

19:36going to expect those to be single

19:38student classrooms. It doesn't make

19:39sense to speak in that way. The

19:41inventions actually,

19:42>> but it doesn't foreclose that

19:45interpretation, does it?

19:46>> I think it comes as close as you can be

19:48without saying flat out, heck, Verba,

19:50this is foreclosed. It's just not the

19:52way we use language. But it's akin to

19:54like if to use analogy, it's akin to

19:55like an innovative bullhorn that'll

19:57direct speech to only one person in a

19:59group.

20:00>> The PTAB's decision in this case was

20:02akin to saying, well, all brohorns do

20:04that. The prior art bullhorns do that

20:06because it might be a group with only or

20:08it might be a set of people with only

20:09one person in it and therefore it reads

20:10on the prior art. It's just not a

20:12natural way to read this language. Why

20:14why if if they wanted your construction,

20:16why wouldn't they say it's transmitted

20:18to only one DDR memory device at a time

20:21within a rank?

20:22>> Pardon? So certainly they could have

20:25said within a rank, but everybody in

20:27this case is proceeding on the basis

20:29that it was we're talking about what's

20:31in a rank, right? you've already

20:32selected the rank because C talks about

20:35selecting one or two ranks and then you

20:37say wherein we're going to one device at

20:39a time and the only question is does it

20:41have that trivial case that kind of edge

20:44case of somehow you have a rank that

20:46only has one device in it and that's

20:48just not normal in modern memory systems

20:50and it you wouldn't read this language

20:52to be trying to reach that abnormal case

20:54of a classroom of one student. What if

20:56we were to read column 8 as uh

20:59contemplating a a

21:03single memory device rank?

21:05>> Column 8, your honor.

21:07>> Yeah, that was what uh the board relied

21:10on that along with figure 6B. Yeah. So I

21:12think

21:12>> as examples in the patent specification,

21:15right,

21:16>> of ranks with only one memory device.

21:18>> I think actually points exactly the

21:20opposite way. So column eight column 7

21:22has the logic table and it says logic

21:25table is selection among ranks of memory

21:28devices 30 and if you look at all the

21:30pictures of memory devices 30 they're

21:31all multiples but going further if you

21:33go to column 8 line 30 it says in logic

21:36state 4 and that's the one ones it

21:38discusses later CS is low blah blah blah

21:40thereby selecting rank two so logic

21:42state 4 has selected rank two one rank

21:44only and that's rank two if you move

21:46down it says and this is line 48 in

21:49certain embodiment The command signals

21:51passed through to the selected rank only

21:53state four of table one. So that's rank

21:56two. In such embodiment, the command

21:58signal is sent to only one memory device

22:00or the other memory device. So that data

22:02is supplied from one memory device at a

22:04time. That's selecting one rank and then

22:06you sent it to one memory device or the

22:08other memory device. That doesn't make

22:10sense. You wouldn't speak that way if

22:11you had selected a rank that had only

22:14the paragraph.

22:15>> Right? In other embodiment, the command

22:17signal is passed through to both

22:20associated ranks, eg state six of table

22:23one. In such embodiment, the command

22:25signal, eg refresh, is sent to both

22:29memory devices to ensure that the memory

22:31content of the memory devices remains

22:32valid over time.

22:33>> Yeah. And I think given what came before

22:35it where you're talking about a single

22:37rank sent to one or the other and this

22:39has two ranks. When it says to both

22:40memory devices, it means both memory

22:42devices within the rank. It doesn't mean

22:44you're going to send it to two two ranks

22:46and there's just one memory device in

22:47each. It's just not a natural way to

22:49read it, especially given the prior

22:51statement where it says you're going to

22:53send it to only one rank. In such

22:55embodiment, you send it to one memory

22:57device or the other. That makes sense

22:59only if there's two. In fact, it doesn't

23:01make any sense. The the send it to one

23:04or the other doesn't really make sense.

23:05Um because table one actually has four

23:07ranks. If you were actually just

23:09selecting a rank of a single device, you

23:11wouldn't say send it to one or the

23:12other. You'd be sending it to one of

23:14four.

23:14>> Yeah. The comm the command signal is

23:16being passed to both associated ranks,

23:20right? So, we're dealing we're dealing

23:22with two ranks and then we're talking

23:24about, hey, we can send uh the command

23:28signal to both memory devices in both

23:32ranks. it if it sounds like it's saying

23:35we can have two ranks each rank having

23:38its own memory device and instead of

23:40sending the command signal to just one

23:42memory device we can send it to the the

23:46memory device the only memory device of

23:49both of these ranks

23:50>> no I think it's more naturally read

23:51judge 10 especially given the preceding

23:53example where you're sending it to one

23:55memory device or the other memory device

23:58in a single rank that this means you're

24:00going to send it to both memory devices

24:03in a rank, not send it to one memory

24:07device in each rank. Um, remember these

24:09are two these are states for the same

24:11system. And so you're not going to have

24:13one which is, you know, state four which

24:15is talking about a device that has or

24:17excuse me, a memory that has two memory

24:20devices or four memory devices. And then

24:22the second example, another state

24:23somehow reduces it down to just two

24:25memory devices. It's always going to be

24:27the same number of memory devices. And

24:29the first one is very clear. Example

24:31four is unambiguous that you're talking

24:32about sending it to one memory device at

24:35a time when you're sending it to one

24:38rank, one memory device or the other

24:41when you have a single rank selected.

24:43And you just wouldn't say I'm going to

24:44send it to one or the other in a single

24:46rank if the rank only had one to begin

24:48with. It just doesn't make sense.

24:49There's nothing ambiguous about that.

24:52And then I guess Judge Ten, you referred

24:54to one other item that the board relied

24:56on and I can't quite recall what it was.

24:57>> It was figure 6B. Ah yes figure A and B.

25:01>> Yeah. So figure 6B I think there's two

25:04significant issues with that. Um and I

25:07want to get to like the second one more

25:09quickly but the first is if you look at

25:10the description of 6B and this is page

25:1292 the appendex column 24 lines 26 to 27

25:17and again later on line 32 it talks

25:20about memory devices. It says it's

25:22talking about collisions between data

25:23spurs from one rank of memory devices to

25:25another rank of memory devices. And it

25:27refers to on line 32, memory devices 30.

25:30If you look at page 63 of the appendix

25:32and 64 and 65, memory devices 30 is

25:34always multiples. You've never seen

25:35less. But the more important part, and

25:37this is something the PTAB missed. This

25:39is talking about data collisions, right?

25:42It's how to avoid these data collisions.

25:44If you turn to page nine of our brief,

25:46there's a chart, there's a little

25:47diagram, very simplified diagram there

25:49showing two ranks, rank zero and rank

25:52one. And you'll see that each rank each

25:56DRAM pairing in those will share a data

25:59line. It's of the X8 or by 8 right

26:02there. So you have the possibility of a

26:04data collision between DRM 1 and DM 2

26:06and DM 2 and DM2 DM 3 and DM 3. But you

26:10wouldn't have a collision between DM1

26:12and DM 4. They don't share a data line.

26:14And so when you're talking about the

26:16solution in this context, which the

26:18solution to data collisions, you're only

26:20going to be worried about the collision

26:21between DRM one and DRM one, rank one

26:24and rank zero. And so that's why it's

26:27going to home in. And it says, look,

26:29here's how you avoid a data collision

26:31between these two. In fact, it'd be a

26:33little confusing to go further and say,

26:35you know, um, we'll talk about DRM 2 and

26:38DM 3 because only one pairing can have a

26:41collision at a time. only one pairing

26:43has shares a line. And so since this is

26:46talking about avoiding collisions, you

26:48only look at DRM one and DM one. And

26:51you'd apply the same solution, just

26:53repeat the exact same thing, rinse

26:54repeat for DM 2, DM 3 in each of those

26:58pairings. And the board just missed

26:59that.

27:00>> Your argument sounds like expert

27:01testimony about how to interpret the

27:04patent.

27:05>> Right.

27:06>> Well, this is this is a intrinsic

27:09analysis of it. And the question is did

27:12the board get it right when it says

27:13right up front memory devices 30 and it

27:16refers memory it says memory devices in

27:18a rank plural and when it's talking

27:21about data collisions and you don't have

27:24collisions across DMS you can see it

27:26right there they share a line and that's

27:28why you would and you would looking at

27:29this understand ah we're going to share

27:32we're going to solve a collision to DMs

27:34that share a line but that's means you

27:36only look at that one column you're not

27:38going to be looking at all of them all

27:40at once I guess you're assuming that

27:42when the spec talks about memory device

27:44A, memory device B, for purposes of

27:47figure 6B, you're saying, well, they're

27:50only talking about a partial embodiment

27:52here.

27:53>> Yeah, they're talking about, for

27:54example, memory device A might be DM one

27:57and rank zero in that little picture and

27:59memory device B might be DM one in rank

28:01one. I guess the concern I have is

28:02there's nothing in column 24 that really

28:05channels me into saying, "Aha, we're

28:08only looking at a cutout of a larger uh

28:11embodiment." Well, I think it is clearly

28:14looking at a cutout of a larger

28:15embodiment because it's about, and it

28:17says this, it actually says it's talking

28:20about memory devices 30 otherwise

28:23involved in a signal collision. It's not

28:25all memory devices, it's the memory

28:27devices of signal collision. And if you

28:29look at the picture, the picture doesn't

28:30actually even show you your DRS. They're

28:32just not in the picture. So this is just

28:35the ones involved at a me in a

28:36collision. What's involved in a

28:38collision? The DRS that share a line.

28:40Memory A and memory B or DM one and DM

28:43one and rank zero and rank one. It

28:45wouldn't be all of them. You don't

28:46picture all of them because it's only

28:48the ones. And the quote is involved in a

28:51collision.

28:54If I could quickly turn to and hopefully

28:56I'm without going too deeply into

28:58rebuttal um just very quickly that the

29:01written description of the 486

29:02provisional the board said gave only one

29:05reason for saying that sequential logic

29:08does not does not convey a register even

29:10though the board even though Micron's

29:12own expert said normally it describes a

29:14combination of logic functions and

29:15registers and the board gave only one

29:17reason for saying well you the skilled

29:19writers and still wouldn't understand a

29:21register and that One one reason was a

29:242024 website the board dug up itself. It

29:26wasn't subject to adversary

29:28presentation. It's 10 years too late.

29:30And frankly, if we've been given a

29:31chance to respond to it, we'd explain

29:32that it doesn't show that a skilled

29:34artisan would think of. What what if we

29:36read the board decision to

29:39to consult that website really only as

29:41backup evidence

29:44that it didn't need because there was

29:46already other evidence that supported

29:48the finding of no written description

29:52because there was testimony that you yes

29:57you need some kind of storage space but

29:59it doesn't have to be a register. It

30:01could be something that's not a

30:03register, a functionally equivalent of a

30:04register to be sure, but nevertheless,

30:08uh, a non-register story.

30:10>> I think there's two problems. There's

30:12simply no testimony that a skilled

30:13artisan would think of the alternative

30:15to a register without actually thinking

30:17of the register that somehow you would

30:18get there, that somehow this is such an

30:20expansive group or they're so common,

30:22the alternatives are so common. They

30:23only described it. The only testimony

30:25about anything that does this function

30:27is a register. And second, the only

30:29evidence of an alternative that someone

30:31might think to is this um is this uh

30:35website. If you look at that, it says,

30:37"Hey, it could be an alternative."

30:38Doesn't say who might think of the

30:39alternative, what the alternative would

30:40be, how common they were in 2005,

30:42nothing like that. And the only evidence

30:45it gives is this is this 2024 website.

30:48Thank you. If I could reserve the

30:49remainder of my time for rebuttal. Okay.

30:51Thank you,

31:06May it please the court. I'll address

31:07the same two issues that uh that Net

31:09list did. Starting with claim

31:11construction. I think it's noteworthy

31:13that uh in order to get to the

31:15construction of rank that Netlist

31:17prefers, you have to add words both to

31:19the claim itself and to the

31:21specifications description of the

31:23embodiment. Neither of those say that

31:25you send a command to a single device

31:27within a rank. It's simply not there. It

31:30says you send it to a single memory

31:32device. Um uh Netless cited, you know,

31:36ordinary language and and talked about

31:38the the natural reading. I think in this

31:41context, the most instructive, uh uh

31:44evidence on how a person of ordinary

31:47skill would understand the word rank in

31:49this context is the technical definition

31:52in the Jacob textbook. This is at

31:53appendix 11702 which says a rank of

31:57memory is a bank of one or more DRAM

32:00devices. That is the best understanding

32:02of the word rank in this context and

32:05there's nothing in the claim language or

32:06the specification that that provides a

32:09reason to depart from that. On the

32:11contrary, as uh Judge Chen, you pointed

32:13out and as the board found, the

32:15specification describes uh an embodiment

32:18of single device ranks in logic table

32:22one. I think there may be some confusion

32:25about what logic table one is describing

32:27here at appendix 84. So I want to make

32:29sure it's clear. Um there are four ranks

32:32to start with in the states in this

32:34table. But by the time you are sending

32:36to one memory device or the other, if

32:39you've selected one rank or uh both

32:41memory devices, if you've selected both

32:43ranks, there's already been an initial

32:45processing of the chip select signal. So

32:47you can see this in table one for state

32:494. It's only uh chip select one that is

32:53active. So then you uh you are selecting

32:55the two ranks that are associated with

32:57chip select one. And it's in that

33:00context that the patent then says that

33:02the command signal is sent to only one

33:05memory device or the other memory

33:07device. So we're talking about two ranks

33:10and we're talking about selecting one of

33:11those. And when you make that selection,

33:13the command signal goes to only one

33:15memory device or the other. That is a

33:17single device rank. Again, even clearer

33:20is state six where again you see in the

33:22table that uh chip select one is

33:24selected. And so then we're looking at

33:26the two ranks that are associated with

33:28chip select one. In that case, you've

33:31selected both of those ranks and the

33:33command signal is sent to both memory

33:36devices. As the board found, you're

33:38talking about sending to two ranks, two

33:41devices. That means one device per rank.

33:43That is clearly consistent with the

33:45construction of rank that the board

33:46adopted here. Uh I think the uh the

33:50figure six embodiment about the

33:51backto-back adjacent read commands and

33:53preventing collisions is also

33:55instructive as again the board found

33:57based on the record here. Um the diagram

34:01at uh page nine of net list's opening

34:04brief sort of assumes

34:05>> isn't it true the objective of this

34:08invention is to use as many lowcost

34:12memory devices as possible as a

34:14substitute for fewer high cost high-end

34:20uh large memory devices. The objective

34:23of this invention is to multiply either

34:26the number of devices per rank or the

34:28number of ranks per module that's

34:31recited at appendix 86 at column 12 as

34:34well as appendix 81 at column 2.

34:36>> I guess I'm wondering in in this

34:37scenario in the context of this patent,

34:40why why would you ever have a a rank

34:43that only has one memory device? Because

34:45if you have one rank uh if you have two

34:48ranks with one memory device each,

34:50that's still better than one rank with

34:52one memory device. It's it's rank

34:53multiplication. It is expanding the

34:55capacity of the device in one of the two

34:57ways that the patent describes. Again,

35:00uh we're obviously looking at the claim

35:02language, not construing it uh in view

35:04of of the purpose, but we do think that

35:06a single device rank is consistent with

35:09the purpose of this invention because

35:10>> you think it would be unusual to have an

35:13embodiment with just a single rank with

35:16I don't know 80 memory devices.

35:18>> You could not have an embodiment of

35:20claim 16 that would have a single rank.

35:22And that's because of the language

35:24language uh regarding the uh the first

35:29number of ranks and devices and the

35:30second number of ranks and devices.

35:32Right? The second number that's what

35:34corresponds to the input signal has to

35:36be smaller than the the first number. So

35:39that first number is always going to be

35:40at least two. There's always going to be

35:41at least two ranks and at least two

35:44devices.

35:44>> Right? I I'm just thinking just based on

35:47what's being disclosed in this patent

35:49it, you know, there's there's nothing in

35:52here that suggests well, you know, as

35:54long as we get a lot of memory devices,

35:56it could be a single rank with a endless

36:01row of memory devices. And my my point

36:04is it seems like they're they're they're

36:07looking to try to increase, you know,

36:10really pump up the numbers of memory

36:12devices. And you can do that through

36:14many many ranks and you can also do that

36:16with many many devices in a given rank.

36:19>> You're trying to expand capacity. It's

36:21true. The patent again column 2 lines 24

36:24to 28 talks about two different ways to

36:26do that. You can either multiply the

36:28number of devices per rank or you can

36:30multiply the number of ranks per module.

36:33and going from a one rank module to a

36:37two-rank module is a multiplication even

36:39if each of those ranks has only one

36:41device on it. Uh the fact that the the

36:44patent talks about for example um you

36:47know using lower density devices

36:50multiple lower density devices in those

36:52ranks maybe that achieves some further

36:54purpose economically but the claim says

36:56nothing about that. It doesn't require

36:58anything about the respective density of

37:00the devices or the ranks. It just says

37:03you have to have a first number of ranks

37:05and a first number of devices that is

37:07larger than the second number of devices

37:09and second number of ranks. I realize

37:11the it's a little confusing because the

37:12second one is what's coming in but I I

37:14think take the point your honor.

37:17I would also uh so going back to the the

37:20um the diagram at at uh page nine of

37:23netless opening brief and the argument

37:25about uh collisions again using that

37:27diagram assumes the conclusion. and it

37:30assumes that we're already operating

37:32within a rank that has multiple devices.

37:35If you have two ranks that each have one

37:37device in them, there is still a

37:39collision risk and there that can still

37:41be addressed by the uh technique

37:44described in with respect to figure six

37:46of using these uh FET switches to

37:49isolate the the DQ strobe signals of the

37:52two devices. And again the patent at

37:55column six, excuse me, at at column 24

37:58at figure six uh says there are two

38:01ranks and talks about two memory

38:03devices, memory device A and memory

38:05device B as the board found that is

38:07further intrinsic evidence supporting a

38:10construction of rank to be just as the

38:13textbook says one or more devices.

38:17If I can turn to written description um

38:20on the 436 patent a few points your

38:24honors I I think there was a bit of a

38:27mischaracterization of

38:29the record um as the board found both

38:33experts

38:34>> and by the board's independent

38:36consultation of a website and then

38:38relying upon it. No, we have agreed that

38:40that was improper. Um, but it was not

38:42essential to the board's analysis. And

38:44so under this court's decision in Nike,

38:46for example, um, that's not enough

38:48reason to, uh, to vacate the board's

38:51opinion. The board's conclusion that

38:54there was no written description support

38:55in the 436 patent for a register was

38:58supported by substantial evidence.

39:00Again, in the testimony of both experts,

39:03I I think netless experts testimony, as

39:06the board found, is particularly

39:07instructive. Dr. Bjoli said that to do

39:10the sequential logic, right? That's the

39:12hook they have in the 436 patent. It

39:14describes that it can do sequential

39:16logic and they say, "Well, that require

39:18a person of ordinary skill would know

39:19that's a register." No, their own expert

39:22at appendix 18345

39:24said it would require a storage or

39:27register. Storage is even broader than

39:30uh than a register. So, he certainly

39:32didn't think that a register was

39:33required. And of course, our expert at

39:35appendix 18693 did not say you needed a

39:39register. You would envision a register.

39:41What he said was it requires state

39:43storage in the form of a register or

39:45equivalent. A sub equivalent language

39:48may be enough. We don't require in hike

39:50verba disclosure but substantive

39:52equivalents are not enough. In fact, in

39:54the Nelroprian case, uh, which Netlist

39:57has relied on, this court made an

39:59exception there, but still reiterated

40:01the quote that the rule that as a

40:04general matter, written description may

40:06not be satisfied by so-called equivalent

40:08disclosure on the peculiar circumstances

40:11of that case. Is it possible that

40:14what the 436

40:18U provides support for is a register or

40:23an equivalent of a register that in in

40:26in that way the inventors were in

40:28possession of that entire set. We know

40:31that these logic elements need some kind

40:33of temporary storage space that just

40:35comes with the territory.

40:37And there were at least a handful of

40:40very well-known little devices that

40:43could perform that very common function.

40:47One of them was a register and then

40:49equivalents. It's kind of like a

40:51fastener could be a screw or a nail or

40:55something else. They're all super

40:57interchangeable. And

40:59>> why wouldn't um you have possession of

41:03all of those kinds of fasteners just

41:06like you would have

41:08uh possession of all the different kinds

41:09of known little temporary storage spaces

41:13that include registers, flip-flops, etc.

41:15>> That's not the law for written

41:16description, right? The hallmark of

41:18written description is disclosure. I

41:19think this court's decision in the

41:20null's case is particularly instructive

41:22here. There the claim was to a solder

41:24reflow process. Uh and what the uh

41:28earlier uh application disclosed was

41:31just a method of connecting pads to a

41:33circuit board. Solder reflow was one

41:36known way of doing that, but there were

41:37other known techniques as well. This

41:39court held that's not written

41:40description for it. I think we have

41:42exactly the same situation here. Looking

41:44at the the disclosure of sequential

41:46logic in the 436 patent. Yes, maybe you

41:49would know that you could use a

41:51register, but you would also know as

41:52both experts here agreed that you could

41:55use something that wasn't a register.

41:56That's not written description support

41:58for a register. Regardless, I'd like to

42:00>> claim instead of registers that said

42:02storage space.

42:04>> Maybe we'd have a different case, but it

42:05doesn't

42:06>> be a different case.

42:07>> It would be a different case, but that's

42:08not what we have here. We require a

42:10particular component, which is a

42:12register. It's not disclosed. And of

42:14course, the court need not even reach

42:16that issue because the board had two

42:18other bases for rejecting written

42:20description on the 436 patent. And one

42:23of them was net list's failure to meet

42:25its burden under this court's case law

42:28to to once uh the petitioners had cited

42:31Ellsworth's prior art and met their

42:33initial burden of production, the burden

42:35of production transferred to net list to

42:37show written description support for all

42:39limitations of claim 16. Net list hasn't

42:42disputed that that is what this court's

42:45case law requires. I don't think they

42:46could given the language of tech

42:48licensing, for example.

42:50They argue only that there are a handful

42:52of board decisions, non-presidential.

42:55They call it precedent. They're not

42:56presidential opinions. Board decisions

42:58that suggested otherwise. I'd say a few

43:01things in response to that. First of

43:02all, obviously, even if there there were

43:04such decisions, they can't override this

43:06court's case law. More importantly,

43:08>> are you contesting that there were other

43:10limitations that lack written

43:12description support in the 436?

43:14>> We uh we have contested that, but the

43:16important point is we didn't have to. We

43:18had no burden to specify in the petition

43:21uh which ones we thought were um uh were

43:25not disclosed and then they only had to

43:27address uh those. That's what the board

43:29said in the Lupin decision. And then

43:31later in the Max light case in 2021, the

43:34board in a reharing decision came back

43:36and said Lupin's not right. That's not

43:39the rule. That is not consistent with

43:41federal circuit case law. And since that

43:43time, the board has not departed from

43:45that principle. More importantly in this

43:47case at appendix 879 at institution net

43:50list was told by the board talking about

43:53the 436 patent specifically that they

43:56needed to uh um

44:00to show written description support for

44:03all subject matter and that they had

44:05instead addressed only particular

44:07limitations. Again that's 879.

44:10And then netlist didn't object. Instead,

44:12they accepted that burden at appendix

44:151016 in their patent owner response.

44:18They acknowledged that the board had

44:19imposed that requirement. They didn't

44:21argue this is wrong. They didn't argue

44:23this is inconsistent with other board

44:25precedent. They didn't cite the loop in

44:27case. They recognized it was their

44:29burden. And as we've pointed out, they

44:31attempted to meet it for the 244

44:33provisional. They failed for the reasons

44:35the board has found. And I did not hear

44:37that topic addressed in opening, so I

44:39won't go into it. They didn't even try

44:41for the 436 patent. The law is clear.

44:45They haven't disputed what this court's

44:46case law requires. They were told what

44:48they had to do. They acknowledged what

44:50they had to do and they simply didn't do

44:52it. And that's a sufficient basis to

44:54affirm the board's finding of no written

44:56description support in the 436 patent.

45:01If the court has no questions, we'd ask

45:03the court to affirm the board.

45:04>> Okay. Thank you, Mr. Lamco.

45:15Thank you. If I could begin with the

45:16Jacob's test textbook that actually

45:19shows exactly why skilled artisans would

45:21not interpret this invention which is

45:23about expanding me memory capacity by

45:25using smaller memory devices but more

45:27numerous ones would somehow have a

45:29single device rank and it explains that

45:32it says first for modern memory systems

45:34you typically have multiple DRM devices

45:36that's at 1173 and it goes on and says

45:39the term is now used to denote quote a

45:41set of DRM devices that operate in lock

45:43step when there's one there's no block

45:45step. In fact, it goes on and gives the

45:47one example of when you might think you

45:49might have a a rank of one and it talks

45:52about a embedded system that does not

45:54require much capacity. A skilled artisan

45:57reading this patent is not going to

45:58think we're talking about that edge case

45:59of the embedded system that doesn't need

46:01capacity. This is about high-end server,

46:04high-end computer RAM that where we're

46:07trying to expand the memory capacity,

46:08not only by having more DRAMs per rank,

46:10but expanding upward as well and having

46:13more more um ranks. Um, do you disagree

46:18that it was netless burden to show

46:20written description support for all

46:23limitations in the claim?

46:25>> No, your it's not our burden to show it.

46:27We had a burden of production, but not a

46:29burden of persuasion. And then so it

46:31always the burden of persuasion is

46:32always on the other side. But the burden

46:34of production isn't for all of them. I

46:35think under Lupin and the cases

46:37post-dating Max light there's other

46:38cases from there from the board saying

46:40no you only have to respond to the very

46:43things that were pointed out and we

46:45followed that and I think the and uh

46:48when council points to page I think is

46:49840 or 879 and says oh they told you you

46:53have to respond to everything. Actually,

46:54if you look at 878 877, that's where the

46:57board actually goes through the specific

46:59articulations, the specific things that

47:02Micron is pointing to. And then it says

47:04you have a burden of response.

47:06>> Excuse me. Well, it's that is in the J

47:09>> 877 878.

47:11>> Okay. Then it's I'm talking about 488.

47:14Yeah. Um it's 487. I think we just

47:17you're using the wrong numbers. So the

47:18assertion that council was citing is on

47:21488. We just had the wrong number. And

47:24486 and 487 are where they go through

47:26and say it did not. The other side

47:28Micron argues it did not disclose a

47:30logic element. It didn't uh disclose a

47:33circuit comprising a logic element and

47:34and a register. And then the board says

47:37the burden of production shifts to

47:38patent to show. It's not a textual

47:41saying and everything else in the

47:42universe. It's just the ones that were

47:44raised on 486 and 487. Um,

47:48>> is that the reason why you only did the

47:51peace meal um, presentation for That's

47:54right. You know, on 436, but for the 244

47:58provisional, you went all the way soup

48:00to nuts.

48:01>> Yes. Making a full-blown presentation

48:04for every limitation.

48:05>> Some sometimes they you if you have the

48:07pages, sometimes you're more thorough.

48:09And if there's any confusion there, it's

48:10because there's different board

48:11precedent going different ways. You have

48:13that one case, the MaxLite case, cited

48:15in the middle, but there's cases before

48:16loopin and cases after Max light that go

48:18the other way. And it's just arbitrary

48:20and capriccious for the board to choose

48:21one set of cases for one case and

48:23another set of cases the other case. It

48:25has to have a rule and it has to follow

48:27that rule consistently.

48:29>> I think we're out of time.

48:30>> Thank you so much.

48:31>> We ask that the court reverse. Uh our

48:34next case is number 251286

48:37listing versus Samson electronics.

49:27Okay, Mr. Nolan.

49:40Thank you your honors and may it please

49:42the court. The boy the board legally

49:46erred here in adopting an obviousness

49:48theory that required dismantling the

49:50memory modules of Parago a Rambus patent

49:54and then rebuilding them to comply with

49:56the fundamentally different Jadeex

49:58standard. And that legal error follows

50:00from three facts about the proposed

50:03modification, all of which are

50:05undisputed.

50:06The first fact is that the modification

50:09renders Parago's modules nonfunctional

50:12in the RAM architecture for which Parago

50:15was designed. The second fact is that

50:18the modification eliminates the

50:20configurable width nature of Parago's

50:23buffers because JDK compliant modules do

50:25not have a configurable width. And the

50:28third fact is that the modification

50:30destroys the buffer's ability to

50:33translate between memory controllers and

50:36memory devices that would not otherwise

50:38be compatible with one another. In

50:41short, this theory that the board

50:44adopted, it basically eliminates the key

50:48innovations in Pereago's module. And so

50:51this is a case where the undisputed

50:53facts, including some facts that the

50:55board expressly found, demonstrate that

50:58the board's legal conclusion was wrong.

51:01The analysis is flatly inconsistent with

51:04this court's inoperability and intended

51:06purpose cases like Metronic, Kors,

51:09Polaris, and the others cited in our

51:11brief. Now, I want to focus for a

51:13moment.

51:14>> I don't read the our cases the same way

51:17that you do. I mean the axonics and your

51:19Vansky cases make clear that the

51:22question is whether the combination will

51:24serve the purpose of the patented

51:26invention not whether it will serve the

51:28purpose of some piece of prior art from

51:31which one of the elements is taken.

51:35Well, your honor, respectfully, Erbansky

51:38actually reaffirmed the legal rule that

51:40we're relying on that that we don't

51:43accept modifications of the prior art

51:45that render them inoperable for their

51:47intended purpose and simply found it not

51:49satisfied on the facts there. um the the

51:53Axonics case that that your honor cited

51:55it it acknowledged um and I acknowledge

51:58that the intended purpose of the prior

52:00art doesn't always control but this

52:02court reaffirmed in the Medronic versus

52:04Telelex case that the obviousness

52:07analysis does have to consider whether

52:10the modification that is being proposed

52:12is going to frustrate what the prior art

52:14reference is setting out to do. And this

52:17court in that case in Medtronic

52:19expressly rejected a reading of Intel

52:21which is another case that Micron has

52:23relied on that would say that the

52:25intended purpose of the prior art is

52:26simply irrelevant. And here you have

52:29basically three benefits that Pereago is

52:32talking about. It's got a high

52:34performance RAM primary channel. It's

52:36got a buffer that's configurable width

52:39so you can do it at 128 64 32 and so on.

52:43and it's got a buffer that has this

52:44translation functionality that allows

52:46otherwise incompatible memory devices

52:48and memory controllers to talk to one

52:51another. This modification throws all of

52:55that away. It is then that is

52:57undisputed.

52:58>> There's another stated goal of

53:01upgradability,

53:03>> right? And

53:04>> correct. and doing this modification to

53:06make it JDK compliant. There's an a

53:10basis to say that there would be uh an

53:13upgrade by doing that.

53:15>> Well, in fact, your honor, I think it's

53:18undisputed that it would not be

53:20upgradable if you make the module JDK

53:22compliant because once it's JDK

53:24compliant, then the module no longer has

53:27the ability to translate between

53:29otherwise incompatible memory

53:31controllers and memory devices. And also

53:33the module no longer has the ability to

53:36dynamically configure the width to

53:38different values while the module's in

53:40operation. So you're

53:42>> it why is it so I mean it seems to me

53:44there's some indisha in the parago

53:48reference that suggests

53:51being a Jade compliant. For example, it

53:55talks about

53:57uh in alternative embodiment, not the

54:00embodiment that uses pointto-oint links,

54:03but in alternative embodiment, you can

54:06use strobe signals with a bus. Um you

54:11can also have this configurable buffer

54:14data width of a magnitude that's more in

54:19the JDex sphere rather than the VMus

54:21architecture.

54:23So I guess why aren't things like that

54:26suggesting this isn't such a narrow

54:30exclusively rampous architecture as as

54:33you're advancing when Perego is giving

54:36us clues right in its disclosure that

54:40really channel more towards a JD

54:43compliance scheme. So let me address the

54:46the row address strobe and column

54:48address strobe lines first and then I'll

54:50talk about the 64-bit

54:51>> RAM architecture use those strobe

54:53signals.

54:54>> It doesn't but the key is and and this

54:56is a fundamental fact that I think the

54:58board misapprehended

55:01does disclose JDK compliant memory

55:04devices which are the individual chips

55:06that reside on the module and you can

55:08see the distinction at the figure of

55:10page seven of our blue brief. The chips

55:12are the little black pieces that are on

55:14the module. The module is the entire

55:16printed circuit board which has all the

55:18chips on it. What Parago says is that

55:21precisely because its buffer has this

55:23translation functionality, Parago can

55:27use JDK compliant memory devices without

55:31needing the module to be JDC compliant.

55:35And the reason that Pereago talks about

55:38signal lines that are suggestive of JDK

55:41like row address strobe and column

55:42address strobe is because you do need

55:44those signal lines on the secondary

55:46channel to allow the devices to

55:49communicate with the buffer. What PAGO

55:51doesn't disclose is using those signal

55:53lines on the primary channel which is

55:55what you would need in order to conclude

55:58that Parago is disclosing a JDK

56:00compliant module. And I want to

56:01emphasize something. It's not only that

56:04you don't need a JD JDK compliant module

56:08in order for Paragos's device to work

56:10with these different types of memory

56:13devices. It's that you can't have one

56:16because if you had a JDC compliant

56:18module, it couldn't do this translation

56:20which is central to Parago.

56:22>> Did you have your expert uh describe all

56:24of this detail about how there's a you

56:28know at the device level? Sure, maybe it

56:30can be Jade, but it can't be at the

56:32module level. Module level is something

56:34else. And that so parago is only when it

56:37talks about these various strobe

56:38signals. It's really talking in a device

56:42specific way.

56:43>> Yes, our expert explained this at

56:45length. the the primary discussion that

56:47I would point the court to spans

56:49appendix 11471

56:52to 11477

56:54and that's about paragraph 129 to 139 of

56:57our experts declaration and again the

57:00board didn't dispute this board didn't

57:02say no you're wrong actually JDC

57:05compliant modules do have a translation

57:07functionality I think that the board

57:09fixated on Pereago's disclosure of JDK

57:12compliant devices and thought that that

57:14implied hide a disclosure of JDK

57:16compliant modules which in the context

57:18of Parago just doesn't follow because

57:21Pereago expressly tells you we can use a

57:24JDK compliant device without needing the

57:26module to be JDK compliant. I want to

57:29also address the 64 bit width that you

57:32referred to Judge Chen.

57:34The fact that Parago's module can be

57:37configured to a bit width that just so

57:40happens to coincide with one of the JDEX

57:42standard bit widths does not answer the

57:45problem because again it's undisputed

57:48that if you make a module JDK compliant,

57:52it's not going to be configurable width

57:54anymore. It's going to have a single

57:56width. And so you lose this

57:58upgradability and this compatibility

58:00with different generations of memory

58:02devices and memory controllers that

58:05Pereago emphasizes is central to its

58:08invention.

58:09And the board didn't address any of

58:12this. Not only are the facts undisputed,

58:14the board did not even acknowledge it.

58:16and and Judge Dyke, even if you think

58:18that uh that this court's cases don't

58:22require the intended purpose of the

58:24prior art to control, I think cases like

58:27Medronic versus Telelex and Polaris are

58:30very clear that it's at least a relevant

58:32fact that the board has to grapple with.

58:35Yeah, that may be in some circumstances

58:37where you're

58:39uh taking a particular feature um uh

58:43from the prior art and and you're you're

58:46saying that that feature should function

58:48the same way that it did in the prior

58:50art, but we're not dealing necessarily

58:52with that kind of situation. The Gordon

58:54and and Frri cases on which you so

58:57heavily rely

58:59back to a time and they they say it

59:01explicitly that you had to find the

59:04motivation to combine in that particular

59:06piece of prior art. That's no longer the

59:08case after KSR. You can look uh

59:11elsewhere and that's what the board did

59:14here.

59:15>> Agreed. But you still have to have a

59:18reason to do the modification in the

59:20first place. And and I read subsequent

59:23postks cases like Medronic versus

59:27Telelex, like Polaris, like even Intel,

59:29the case they rely on to say you even

59:32post KSR, you've got to account for what

59:35you're doing to the primary reference.

59:37And if you're frustrating the ability

59:39>> sense, I mean, the whole purpose of of

59:41picking and choosing elements from the

59:43prior art is that you're taking them out

59:46and and using them for a different

59:48invention and a different purpose. Uh it

59:51can't be that it has to serve the

59:54purpose of the invention from which you

59:56selected that element because you've got

59:58a different invention here. And the

1:00:00question is whether there's a motivation

1:00:02to combine the two that is found in

1:00:05general or in other prior art or

1:00:07whatever that's just and that and I

1:00:09think exonics makes that pretty clear

1:00:11that that's what the purpose is.

1:00:13>> So respectfully your honor I want to

1:00:16make two points in response. One is that

1:00:18I think it does make sense to have some

1:00:20version of a principle of operation

1:00:22doctrine because it avoids hindsight and

1:00:25that's precisely the reason this court

1:00:26adopted the doctrine in the first place.

1:00:29This was a convoluted obviousness theory

1:00:31that required starting with Parago just

1:00:34because it had a data buffer, something

1:00:36that JDK compliant modules didn't have

1:00:39and that Parago expressly says JDK

1:00:41compliant modules didn't have and then

1:00:44you dismantle everything, keep the

1:00:46buffer and then rebuild it in a way that

1:00:49serves none of the purposes that Parago

1:00:52was designed for. That is transparently

1:00:54hindsight. And the second thing I want

1:00:56to say is even if your honor and I

1:00:59disagree about where the line is,

1:01:02there's got to be a line somewhere.

1:01:03Because if there weren't, cases like

1:01:05Kimors could not have come out the way

1:01:07that they did. Cases like Polaris where

1:01:10the board just didn't grapple with the

1:01:12fact that the modification to the ATV

1:01:14would raise its center of gravity. Those

1:01:16cases couldn't have come out the way

1:01:18that they did.

1:01:19>> In in Polaris, for example, you're

1:01:21you're keeping that feature of the prior

1:01:23art. And if

1:01:26so, you're necessarily going to ask

1:01:28whether that feature continues to work.

1:01:31>> Well, here if you're not taking that

1:01:34feature from the prior art, then whether

1:01:37it uh would work to achieve the earlier

1:01:39purpose seems not beside the point.

1:01:42>> But your honor, you are keeping that

1:01:43feature of the prior art. you are

1:01:44keeping the buffer which is the thing

1:01:47that is doing the translation

1:01:49functionality and the configurable width

1:01:51that Pereago talks about repeatedly. So

1:01:54you are keeping that functionality and

1:01:56you're just completely neutering it. And

1:01:59I would submit that that's not a viable

1:02:01obviousness theory and regardless of we

1:02:04might have differences on where we think

1:02:05the line should be drawn as to how much

1:02:08the purpose of the prior art should

1:02:10should impact the analysis. But I think

1:02:13that the cases I've been citing in my

1:02:15argument show that they at least have to

1:02:17be considered and the board did not do

1:02:20that work here. The board did not

1:02:21consider these uh these problems, this

1:02:25loss in functionality that you would

1:02:27have if you made this modification of

1:02:28Pereago that requires at the very least

1:02:31vacator and remand. But we think because

1:02:33the facts that underpin our argument are

1:02:35undisputed that the court should

1:02:37reverse. I see I'm intimate.

1:02:38>> On what basis are you sort of concluding

1:02:42that the intended purpose is limited to

1:02:46the Ramis architecture? Because you're

1:02:48not you're only taking certain features.

1:02:52I think this is the point Judge Dyke was

1:02:55making. You're taking certain features,

1:02:56certain teachings

1:02:58from Perego and applying them in the

1:03:02obviousness context and not necessarily

1:03:06limited

1:03:07to the Rambus architecture.

1:03:10>> Well, sure, but even if Pereago is not

1:03:12limited to the Rambus architecture,

1:03:14Pereago's entire disclosure is focused

1:03:17on the configurable width nature of the

1:03:20buffer and the fact that the buffer has

1:03:21this translation functionality. And it's

1:03:23undisputed that those two things would

1:03:25be lost if you make this modification.

1:03:29My argument would be that the the

1:03:30intended purpose of Parago is you have a

1:03:33configurable width buffered module that

1:03:35can translate between otherwise

1:03:37incompatible controllers and devices and

1:03:39it uses a high performance RAM channel.

1:03:41And I would note parenthetically that's

1:03:43basically what Micron's expert said

1:03:45below. That's how he characterized

1:03:47parago.

1:03:47>> That seems to me to be just another way

1:03:49of saying it's limited to the RAM

1:03:51architecture. Well, not necessarily,

1:03:54your honor, because

1:03:55>> the board looked at it that way and

1:03:57certainly it doesn't appear that way to

1:03:59me.

1:03:59>> So, this goes back to the point I was

1:04:01discussing with Judge Chin, which is

1:04:03Pereago is not limited to RAM in the

1:04:05sense that it permits JDK compliant

1:04:07memory devices to reside on the module.

1:04:10And so, it does disclose some circuitry

1:04:12that permits those JDK compliant devices

1:04:15to function. What Pereago doesn't

1:04:17disclose is the JDAC compliant interface

1:04:21at the module level as opposed to the

1:04:23device level. To the extent the board

1:04:25found otherwise, we think that that

1:04:27lacks substantial evidence. But even if

1:04:29you disagree with me on that, there's

1:04:31still this problem that if you make the

1:04:33modification, you are neutering the two

1:04:36benefits, the configurable width nature

1:04:38and the translation functionality that

1:04:40PGO emphasizes. Board didn't address

1:04:42that and we think that that should be

1:04:44dispositive here. Okay.

1:04:46>> Okay.

1:04:46>> If the I see I'm out of time. If the

1:04:48court has

1:04:49>> two minutes for rebuttal.

1:04:50>> Thank you, your honor.

1:04:52>> Mr. Minhaus.

1:04:58>> Good morning. May it please the court. I

1:05:00want to pick up just where we left off

1:05:02which is I think net list is pressing

1:05:04the idea that Paraggo is limited to

1:05:06Rambus in the sense that the module the

1:05:08interface with the controller must be

1:05:10Rambus. But of course the board found

1:05:12the opposite at appendix 28 and there

1:05:15was no confusion about devices versus

1:05:18modules. I want to point to two of the

1:05:20key reasons that the board gave. One is

1:05:22that um as council conceded perigo talks

1:05:27about an alternative embodiment to

1:05:28packetized signals um that involve row

1:05:33address strobe and column address strobe

1:05:35uh control signals. Those are

1:05:37indisputably not part of a rambus

1:05:39architecture at the module level. And

1:05:41that's what the board found at appendix

1:05:44uh 25 to 26. Row address strobe RAZ and

1:05:48column address strobe Cass are Jedex

1:05:50module inputs module inputs not RAM

1:05:54signals. And similarly at at 2 at 26 the

1:05:57board said it's characteristic of a

1:05:59Jedex style RD dim which is a module not

1:06:02a device.

1:06:03uh council has no response other than to

1:06:05assert that the board was confused about

1:06:07devices but there rambis modules cannot

1:06:09use these signals and that's what um

1:06:12their expert conceded at uh 8236 34

1:06:17um and there's obviously plenty of other

1:06:19evidence the board cited the other

1:06:21reason I wanted to give is the 64-bit

1:06:22data width I want to make sure there's

1:06:24no confusion about that these findings

1:06:25are at appendix 23 to 25

1:06:29a rambus module is undisputedly the

1:06:32greatest module width bitwidth it can

1:06:34have is 32 to 366 bits. So it cannot use

1:06:38RAM what Paraggo discloses of a 64bit

1:06:41width module. Um and Paraggo even goes

1:06:44to 128 that's what the board found

1:06:47that's about the module not the device

1:06:50that's about the module. So that

1:06:51implementation that module cannot be

1:06:53used with the RAM module that implodes

1:06:56uh netless entire theory because netless

1:06:59entire theory is ago is through and

1:07:01through. It has to be Rambus at the

1:07:02module level. But the board found no.

1:07:05Paraggo actually discloses embodiment

1:07:08that comply have jet compliant features

1:07:10that cannot be used with a RAM module.

1:07:13Um and then there's obviously the second

1:07:16independent reason which is what I think

1:07:17Judge Dyke was focused on here which is

1:07:19that there's a separate motivation to

1:07:21combine um which is also at appendix 28

1:07:24which is that Jedek was the dominant

1:07:27standard in the marketplace and there's

1:07:30u again their expert has conceded this

1:07:32at appendix 8293

1:07:35he's questioned if it at the 2004 to

1:07:372005 time frame he said absolutely

1:07:40correct that the industry did select the

1:07:43Jedi approach and reject the Rambus

1:07:45approach. And so we're exactly in what

1:07:48Judge Dyke was talking about, the

1:07:49axonics tradeoff scenario. And it's not

1:07:53this is not a case where the board

1:07:54didn't address the trade-off. The board

1:07:55did address the trade-off at appendix

1:07:5728. It said the modifications would make

1:08:00Paraggo system non-functional for

1:08:02Rambus, not for Jedek, which was the

1:08:04dominant memory module style in the

1:08:06market. Given Jedic as the standard, an

1:08:08ordinarily skilled artisan would have a

1:08:09reason to pursue such a known option.

1:08:12That makes sense. There's no it's not

1:08:15much of a trade-off at all to adopt the

1:08:17dominant standard and walk away from

1:08:21again this is only some embodiment of

1:08:23parago, but the paraggo embodiment that

1:08:24are ramb

1:08:27that that that industry standard has

1:08:29been rejected. What if the Paraggo

1:08:32reference instead said

1:08:36this disclosure is exclusively about

1:08:39Rambus architecture

1:08:41and um and it's exclusive to Rambus

1:08:45because I want very specific goals to be

1:08:50achieved and they are achieved through

1:08:52the Rambus architecture period. And then

1:08:55it said everything else that it said. Uh

1:08:58but it didn't talk about the strobe

1:09:00signals and bus lines and all that. Um

1:09:05would this be a different case?

1:09:07>> Uh

1:09:07>> or would you still say, "Hey, Jade Deck

1:09:10was dominant. Who cares what Mr. Pereago

1:09:13thinks? skilled artisan at this time

1:09:16would have looked at this dominant 800

1:09:19pound gorilla jade standard and said

1:09:21we're going this way and we're going to

1:09:24uh just rip out whatever is in paraggo

1:09:28for our own Jada compliant purposes.

1:09:31>> So I don't think it's materially

1:09:33different in that the sense I don't

1:09:34think the outcome would change but

1:09:35certainly the analysis might change a

1:09:37little bit. um to answer the question

1:09:39most directly

1:09:40>> the combination would uh

1:09:42>> directly defeat the express

1:09:45>> I understand

1:09:45>> statements in the

1:09:46>> I understand and so there may need to be

1:09:48an analysis of teaching away there may

1:09:50need to be I mean as I don't think

1:09:53there's an inviable legal rule that just

1:09:55because a prior art reference says this

1:09:57is my purpose

1:09:59not anything else that you can't use the

1:10:01prior art for another purpose I think

1:10:03that's established by Axonics Intel

1:10:05Rathon all these cases even Metronic

1:10:08which Nevist relies on says it agrees

1:10:11with Intel that you can go beyond. It's

1:10:14just that it's not always legally

1:10:15irrelevant to consider the prior arts

1:10:17purpose. And so certainly that's a

1:10:18relevant consideration. It has to be

1:10:20dealt with, but it's not Jedek isn't

1:10:23simply off the table when you're

1:10:25considering Paraggo if Paraggo had

1:10:27hypothetically said I am I am Rambus

1:10:29through and through which Paraggo never

1:10:32actually says. Um and so I think we're

1:10:37but in the case we're in it's just a

1:10:38straightforward application of KSR's

1:10:40market forces rationale. Um and there's

1:10:44also no dispute by the way that the

1:10:47configurable width buffer that they are

1:10:49referencing repeatedly is optional

1:10:52within Pargo. Paraggo itself they

1:10:54concede this at their reply brief at 20.

1:10:57The configurable with buffer isn't even

1:10:59an essential feature of Paraggo in the

1:11:01first place. Is is the buffer feature a

1:11:04paraggo

1:11:05is there something special about that

1:11:07buffer which makes it work only with

1:11:10rambus architecture?

1:11:11>> No, there is a dispute about this and

1:11:15it what is undisputed is that um you

1:11:18could no if you used a Jed module in the

1:11:20paraggo system you could not translate

1:11:23across Jedc to Rambus. That is true and

1:11:25the board recognized that finding at

1:11:27appendix 29 that the modific the

1:11:30combination would make um parago

1:11:33non-functional for rambus but the board

1:11:36found at appendix 27 that and I think

1:11:39judge chen was getting at this earlier

1:11:41that the board sort of read the ideas

1:11:43about upgradability and flexibility more

1:11:45generally. It talks specifically about

1:11:47the backwards compatibility forward

1:11:49compatibility disclosure of paraggo

1:11:50there and says that's a reason to

1:11:52interpret paraggo to uh be open to using

1:11:56Jed and not be limited to rambas which

1:11:59tells you that the board found the board

1:12:01obviously thought that that those

1:12:03advantages would apply to a Jedex

1:12:05system. Now, of course, you couldn't

1:12:08translate across Jedex to RAM. That

1:12:10point is undisputed. True. But so, but

1:12:12the board did expressly consider that

1:12:14trade-off at appendix 29. It said it's

1:12:16nonfunctional for Ambus, but so what?

1:12:18It's still it still would adhere to the

1:12:21do market dominant standard.

1:12:25>> Well, there's no contention that you

1:12:27can't use the buffer for the Jedex

1:12:28standard, right?

1:12:32>> Uh, right. You you could certainly use

1:12:34the buffer for the Jedex standard that

1:12:37um that was found at appendex 40 when

1:12:40discussing the cast limitation the board

1:12:42found

1:12:44>> it was operable operable to together in

1:12:47the jedex

1:12:48>> exactly there's nothing in jedc that

1:12:49prevents you from having a data um

1:12:52buffering on the on data it just was

1:12:54that you have to solve a timing issue

1:12:56and the board found at appendix 40 if

1:12:59you combined paraggo with the jet the

1:13:01jetex standard you would have been able

1:13:03to skilled artisan would have been able

1:13:04to solve that problem. Paraggo in fact

1:13:07discloses the benefit of the buffer

1:13:08which is to reduce load and netless

1:13:12hasn't challenged any of those findings.

1:13:14So that's established. But even scoping

1:13:16out from that, we have these two

1:13:18findings about Argo not being limited to

1:13:21Rambus and it suggests Jedek and that

1:13:23Jedek was the market dominant standard.

1:13:26And in the context of those findings,

1:13:28the board at appendix 27 and 29 clearly

1:13:31weighed the trade-offs. It it found that

1:13:33the Jed uh a Jedek implementation of

1:13:37Paraggo would still have upgrade

1:13:39flexibility and backward compatibility.

1:13:41In fact, that's an affirmative reason to

1:13:43read paraggo is going beyond Rambus. And

1:13:45then it acknowledged, yeah, you would

1:13:47lose this RAM functionality, but so what

1:13:51>> are there certain The other side brings

1:13:53up that there's uh they made a couple

1:13:55arguments that the board never actually

1:13:57addressed and that would be grounds for

1:13:59vacate and remand.

1:14:01>> Well, so that's what I'm precisely

1:14:02trying to get at is that no, the board

1:14:04did address those arguments um at

1:14:06appendix 27 and 29. Um the arguments

1:14:10that were made below were

1:14:13basically this amalgam. It wasn't always

1:14:15clearly presented I think but net list

1:14:17argued that there's this flexibility and

1:14:20it relies on the buffer and this

1:14:22flexibility has different

1:14:24instantiations. You've got this

1:14:25backwards forwards compatibility. You've

1:14:27got this translation across Rambus to

1:14:29Jed and the board addressed both of

1:14:31those sort of parts of the point at

1:14:35appendix 29. It said yeah it's

1:14:36nonfunctional for Rambus. So what that

1:14:38address that side and that in appendix

1:14:4027 it says it you it affirmatively

1:14:44relies on Paraggo's disclosure about

1:14:46upgrade flexibility and backwards

1:14:48compatibility and whatnot to say that's

1:14:51a reason to read it to to to be open to

1:14:54Jed and not be limited to RAM. So the

1:14:56board clearly thought that that

1:14:58functionality

1:14:59um would have application in a Jed

1:15:02system and um you know and there was a

1:15:06dispute about this. I mean, but the

1:15:07board came out in our side. I mean, at

1:15:09appendix 270 to71, that was a petition

1:15:12where we sort of argued the point about

1:15:15how you could have some of this

1:15:16flexibility in Jedek and we cite our

1:15:19expert um that expert testimony is at um

1:15:231556 to 57 uh paragraphs 179 and 181. It

1:15:28also came up at the reply a reply uh at

1:15:31appendix 736 to 37. So, I mean there

1:15:34there was a fight about this. They had

1:15:36their experts say that this stuff

1:15:37wouldn't, you know, you would lose all

1:15:39these benefits, but um there was a

1:15:42dispute about that and the board

1:15:43resolved it in our favor and it's

1:15:45supported by substantial evidence.

1:15:50If the court has no further questions,

1:15:51we would ask that you affirm court. If

1:15:55the court has no further questions,

1:15:57apologies.

1:15:58>> I can't tell you how often that mistake.

1:16:01It's it's rather telling in a sense

1:16:03because

1:16:05council sometimes act as though we are

1:16:07the board and not a court.

1:16:09>> We're a patent examiner.

1:16:13>> Mr. Milton,

1:16:14>> thank you your honors and thank you for

1:16:16restoring my time. Judge Dyke, I believe

1:16:19Micron's council has now conceded that

1:16:22the the purpose of the prior art and the

1:16:24effect that a proposed modification

1:16:26would have on that purpose is, as I took

1:16:28it down, quote, a relevant consideration

1:16:30that has to be dealt with. It was not

1:16:33dealt with here. This was not a factual

1:16:36dispute where they their expert said,

1:16:39"Oh, well, you can modify PAGO's buffer

1:16:41in this way and it still can do the

1:16:43translation. it can still be a

1:16:45configurable with buffer and our experts

1:16:47said no. They've never disputed the fact

1:16:49that if you modify Parago this way, you

1:16:52lose that functionality.

1:16:53>> You don't need that feature of the

1:16:54buffer and accommodation that's made

1:16:57here.

1:16:57>> But you've still got to have a reason

1:16:59why

1:17:00>> you don't need it, right?

1:17:02>> You don't need it to get to the claims,

1:17:04but you do need a reason why the skilled

1:17:07artisan would make the modification in

1:17:09the first place. And that same point, if

1:17:11you don't have that reason, then you're

1:17:14stuck with plain hindsight. And the same

1:17:16point answers Micron's Council's

1:17:18repeated focus on market dominance.

1:17:20Market dominance shows why you might

1:17:22want to have a JDAC compliant module. It

1:17:25doesn't tell you why you would start

1:17:26with Parago and then completely take it

1:17:29apart and rebuild it to get there. Just

1:17:31like there's plenty of market demand out

1:17:33there for Honda Civics, but it doesn't

1:17:35mean that if I want a Honda Civic, I'm

1:17:37gonna start with a Ferrari and keep one

1:17:39piece of it and rebuild the whole car

1:17:40into a Honda Civic.

1:17:42>> But but you might start with Perego if

1:17:44Perego has a teaching that is relevant

1:17:47to and would operate within a JDK

1:17:52environment. Correct.

1:17:53>> Sure. But you can't

1:17:56the the piece that they're trying to

1:17:58take from Parago is the buffer. And the

1:18:01the innovative thing about the buffer

1:18:04which Parago repeatedly emphasizes is

1:18:07that it has this translation

1:18:08functionality and it is configurable

1:18:11with other throwing away.

1:18:14>> It has other features. Correct.

1:18:17>> Nothing that Pereago talks about. And

1:18:19and that and that's the that's the

1:18:21problem. That's why this runs straight

1:18:23into

1:18:24>> you're not using it in the combination

1:18:26for these features you're talking about

1:18:27is using it for other buffer features.

1:18:30Right.

1:18:31>> Sure. But the board still has to

1:18:33consider why would a skilled artisan

1:18:35have done this if by doing this

1:18:37>> that would work in the combination to

1:18:39achieve the patented invention. That's

1:18:41why that's the whole theory of

1:18:43obviousness. But the problem is you're

1:18:46you're starting out with a reference

1:18:47that discloses a buffer, explicitly

1:18:50contrasts its invention with JDK

1:18:52compliant modules which don't have data

1:18:55buffers, and then you're saying, well,

1:18:57you would just take this buffer and

1:18:59notwithstanding everything else Parago

1:19:01says, you're going to drop it in a JD

1:19:03compliant module, even though Paraggo

1:19:05doesn't say anything about how you would

1:19:07solve the timing problems that that

1:19:09would create. That is hindsight and that

1:19:11is why this court's inoperability and

1:19:13principle of operation cases exist. At

1:19:16the very least, the board has to grapple

1:19:18with the sorts of arguments that we made

1:19:20here, which we made at length. They they

1:19:23were they were not abbreviated. They

1:19:24were not confusing. We've cataloged the

1:19:26citations in our briefing. The board had

1:19:28to address it. The board didn't. So, at

1:19:29least we need vacator and remand. I see

1:19:32I'm over time. If the court has any

1:19:34other questions.

1:19:35>> Okay. Thank you. Thank both council. The

1:19:36case

1:19:37>> Thank you, your honor. Our next case is

1:19:39number 251 1936 Net list Inc. versus

1:19:43Micron Technology Texas.

1:20:19You just stay where just stay where you

1:20:21are now.

1:20:52Okay, Mr. Rosen Crrance.

1:21:03Go ahead.

1:21:04>> Good morning, your honors. And may it

1:21:05please the court. Josh Rosen crayons

1:21:07representing Micron.

1:21:09Your honors, this is a nearly half a

1:21:11billion dollar verdict where

1:21:13>> Mr. Rosen CR just hypothetically and I

1:21:16just like to hear it on the record.

1:21:19Hypothetically, if the prior two appeals

1:21:23that we just heard argument on are

1:21:26affirmed, what does that do to your

1:21:30appeal?

1:21:31Well, your honor, in that case, my work

1:21:33here would be done. Um, this court would

1:21:35not have to address uh the the district

1:21:38court appeal. Uh but if the court will

1:21:40indulge me for for a half a billion

1:21:42dollars, I just feel it necessary to get

1:21:44out the main arguments on why the

1:21:46verdict cannot stand even if one or the

1:21:49other appeals. Um

1:21:51>> I want you to do that.

1:21:52>> Okay. Thank you, your honor. Uh so so

1:21:54the half a billion dollar verdict

1:21:56depends upon expert testimony where the

1:21:59experts themselves made concessions that

1:22:03are fatal to both infringement and

1:22:07damages. I'd like to spend my time today

1:22:10focusing on one of the two infringement

1:22:12arguments and on the 912 aortionment.

1:22:17Now, your honors, we briefed two

1:22:18infringement arguments. I'd like to

1:22:21focus on the second. The parties

1:22:24disagree about the outer bounds of the

1:22:27term transmit to. We'll rest on the

1:22:31briefs with regard to what the outer

1:22:33bounds of that term can mean. Our

1:22:36position is it means send to it doesn't

1:22:39mean receive. But for purposes of

1:22:42today's argument I will accept net

1:22:45list's position on the outer bounds of

1:22:48transmit to. Net list says transmit to

1:22:52means that the signal reaches or arrives

1:22:57at the destination. and they disavow any

1:23:00argument that it matters what happens

1:23:02after the signal arrives at or reaches

1:23:05the destination. The undisputed evidence

1:23:08about how our product works

1:23:12confirms that they do not meet Netlist's

1:23:15own definition. I will give the court

1:23:18four facts that netlist has never

1:23:22disputed. First, the command signal goes

1:23:25out on a shared bus. It's one meer, one

1:23:29wire that connects to every memory

1:23:32device in a rank. That's at 20,491.

1:23:36It's at 20,678.

1:23:39Uh, and you could see it in our opening

1:23:41brief at page nine. That demonstr that

1:23:44that demonstrative shows the yellow

1:23:46arrows arriving at every single one of

1:23:49those memory devices. And on the same

1:23:52page, you can see the same thing

1:23:54described in the block diagram.

1:23:57The next three facts are facts that

1:24:00again our witnesses, our experts and

1:24:04technical witness testified to. You will

1:24:06not hear a single dispute about any of

1:24:09these facts from net list uh nor from

1:24:12their experts or or witnesses. They are

1:24:16facts about what happens when the signal

1:24:19is put on that bus. What happens within

1:24:22the device? First, it decodes the

1:24:26command. That's a 20,687.

1:24:30Second, it stores the command. That's a

1:24:3320,859.

1:24:36And then in response to the MRS command,

1:24:40each memory device opens up a right data

1:24:44path. That's at 20,858

1:24:47to 60. This is the path that the DQ0

1:24:52signal travels upon and without that um

1:24:55uh MRS signal arriving there uh and and

1:24:59that path opening up the DQ0 signal

1:25:02never arrives. Now there is actually a

1:25:06fifth fact that cannot be disputed and

1:25:09you could see it in the timing diagram

1:25:12on page 38 of our opening brief. Look at

1:25:16the annotation in the blue box. Net list

1:25:19has no explanation for this annotation

1:25:22in the blue box. And this is the

1:25:24original diagrams about our product.

1:25:27It's not some expert um uh commenting on

1:25:30the product. The annotation in the blue

1:25:32box in the upper right says the MRS

1:25:36command is quote held in the DRAM until

1:25:40the DQ0 signal arrives. Net list has

1:25:44never explained how a jury could find

1:25:47that a device that decodes a command

1:25:50signal, stores it, opens up a data path

1:25:54in response to it, and then holds it

1:25:57while waiting for the next command to

1:26:00arrive, the next signal that is, if the

1:26:03command signal never arrived in the

1:26:06first place. So you're saying the

1:26:08command signal um

1:26:11flows into the input buffer of the non-

1:26:15selected DRAMs.

1:26:18No, your honor. Um there there is

1:26:21another there there is another buffer

1:26:24that net list and their experts are

1:26:27referring to the input an internal input

1:26:29buffer and an internal receiver. No one

1:26:33ever testified to the name of the

1:26:35storage place where the MRS command

1:26:38signal comes in, gets held, gets

1:26:41decoded, uh, and opens up the path. It

1:26:45It doesn't have a name, but obviously

1:26:46it's another uh storage place. I guess

1:26:49if you're waiting for the DQ zero signal

1:26:53to arrive,

1:26:54maybe the command signal for each of

1:26:57these DRMs, it they're just sitting in a

1:27:01waiting room, so to speak, and they're

1:27:03not exactly

1:27:06uh delivered to the DRAM per se, where

1:27:09um you know, or the DRAMs haven't quite

1:27:12yet taken possession of the command

1:27:14signal.

1:27:15>> Your honor, no one ever testified to a

1:27:17waiting room. Net lists brief refers to

1:27:19them sitting at the threshold. No one

1:27:22testified to a threshold. It's a wire.

1:27:24It's got voltage on it. All the

1:27:26electrons go to the DRAM. They may sit

1:27:29in a waiting room, but that waiting

1:27:31room, the only place for them to sit is

1:27:34in the device itself. It then

1:27:38>> okay, but look, what we're dealing with

1:27:41is the meaning of transmit. And I think

1:27:44we're assuming for purposes of this

1:27:46discussion that that transmit means not

1:27:48only sending but receiving. Right.

1:27:51>> Yes, your honor.

1:27:52>> So the question is whether a signal is

1:27:55received before it's received in a

1:27:59usable form. Um and it seems to me that

1:28:04um uh the argument here is that uh it's

1:28:09not received in a usable form until the

1:28:12DQ whatever it is signal comes in.

1:28:14Right.

1:28:15>> Your honor, I I would I would beg to

1:28:18differ about receiving

1:28:19>> sleep until the the sort of the DQ

1:28:21signal wakes it up. the so if I heard

1:28:26you correctly my my answer is

1:28:29that uh the key question is whether it

1:28:33arrives at or reaches the destination.

1:28:36That is net list's definition. You can

1:28:40see it on page 25 and 29 of their brief.

1:28:44Does it arrive at the memory device?

1:28:47It's nothing about usable condition.

1:28:50It's the signal that arrives and it's

1:28:52the signal that gets decoded and that

1:28:55gets held and that um uh that opens up

1:28:58the other

1:28:59>> I'm wondering is I mean we're dealing

1:29:00with a Huelet Packard situation since

1:29:02the parties didn't ask for a more

1:29:04refined claim construction and couldn't

1:29:06a jury conclude that uh it's not

1:29:08transmitted it's not received until it

1:29:11uh is there in a usable form

1:29:14>> no your honor a jury could not conclude

1:29:16that because net list itself tells us

1:29:19over and over again what trans the outer

1:29:23bounds of transmit to. It says quote the

1:29:26ordinary common sense meaning of

1:29:28transmitted to is conveyed to and

1:29:30reaching another place. That's at 25

1:29:33page 29 bolds the phrase reach four

1:29:38three different times in one paragraph

1:29:39to give one example. The claim can be

1:29:42understood as requiring that commands

1:29:45reach the destination i.e. delivery. Net

1:29:49list has conceded at page 30 of the

1:29:51brief that whether they get executed,

1:29:54which is really what's about, what what

1:29:55usable form in your formulation is

1:29:58about, um is irrelevant to their uh

1:30:01interpretation of the claim. Now, I

1:30:03don't want to lose the opportunity to

1:30:05address

1:30:06>> where do they say that?

1:30:07>> Uh at page uh pages 44 to 45 of their

1:30:11brief. quote micron errors when it

1:30:14accuses net list of construing

1:30:16transmitted to as requiring ex execution

1:30:20of the command by by the way their own

1:30:23experts said if you transmit something

1:30:24to an entity it needs to be received by

1:30:27the entity and that that's at 2053231

1:30:36if I may turn to aortionment I I don't

1:30:39want to rush the report.

1:30:42So the the aortionment problems are

1:30:44fatal with both damages award, but I'll

1:30:47focus on the 912 problem which iterates

1:30:50into the 417

1:30:52problem uh w with even greater

1:30:55magnitude. But my basic point, your

1:30:57honors, is that this is Kennedy's MO. He

1:31:01assigns 100% of the same benefit to

1:31:05whatever patent net list puts in front

1:31:07of him. That's not a methodology. It's a

1:31:10contradiction. This can be addressed

1:31:13through the lens of either sufficiency

1:31:16or admissibility. From the lens of

1:31:19sufficiency, the problem arises because

1:31:21net list took 100% of the value when its

1:31:26own expert admitted that he never um uh

1:31:29measured the patent share of that value.

1:31:31Now, net list theory assigns to the 912

1:31:35patent the entire value of getting above

1:31:392400 mega transfers per second. But

1:31:43netless own didn't you cross-examine

1:31:46Kennedy and to try to explore

1:31:49the basis and didn't you try to why

1:31:52didn't you identify I guess what Kennedy

1:31:56had said in a different litigation about

1:31:58the 506 patent? Well, your honor, here's

1:32:00what the here's what we said, what we

1:32:02asked of their technical witness who who

1:32:05provided the basis for

1:32:07>> Yeah, but my my question is much more

1:32:09specific. It's just about Kennedy's

1:32:12testimony in a different litigation

1:32:14about the 506 patent that you think is

1:32:17very very important for a factfinder to

1:32:19understand and evaluate the strength of

1:32:22Kennedy's testimony in this litigation.

1:32:25and you just never raised it during the

1:32:29trial and I don't understand why. Do you

1:32:31have an explanation why that didn't come

1:32:33up?

1:32:34>> I I do. I I see I'm eating into my

1:32:36rebuttal time so I hope I can reserve

1:32:38some. Um so the answer is a very

1:32:41practical answer that the judges

1:32:43standing orders prohibited reference to

1:32:47other litigation. But we got the fact

1:32:50out through the baseline testimony of

1:32:53their technical expert. They we asked

1:32:56their technical expert who supplied the

1:32:58basis for Kennedy this question. In

1:33:01fact, you know, you know that there are

1:33:05other patents that you also believe

1:33:09without them those products wouldn't be

1:33:11able to operate above 2400 mega

1:33:14transfers per second. He says, "Yeah."

1:33:17And then he says that seems reasonable.

1:33:19He also conceded that he didn't consider

1:33:22whether the speed increase was due

1:33:24solely to the 912 patent. And he admits

1:33:27that's not what he was told to do. That

1:33:30is a classic failure of aortionment even

1:33:34if we didn't hit them over the heads in

1:33:37the in the trial testimony though we did

1:33:40in the Dowbert um uh admissibility uh

1:33:44proceeding. uh with this other

1:33:46litigation concession. Uh if there are

1:33:49no further questions, I'd like to

1:33:51reserve the remainder of my time for

1:33:53rebuttal.

1:33:54>> Okay,

1:33:56Mr. Lamin.

1:34:05Thank you, your honor. Because Micron

1:34:08never sought a construction of

1:34:09transmitted to. The question here is

1:34:11just substantial evidence. Could a

1:34:13reasonable jury find that the MRS

1:34:15command is quote transmitted to non-

1:34:17selected DRAMs as a skilled artisan

1:34:20would understand those terms and a

1:34:23skilled artisan could understand that

1:34:25transmitted to requires it to be

1:34:27addressed to and received by and the

1:34:30jury could and there's ample evidence

1:34:32that in the views of skilled artisans

1:34:33>> but what does received by mean here

1:34:35because as I understand the undisputed

1:34:38testimony the signal does get there

1:34:41>> it just doesn't get there in a usable

1:34:42form until

1:34:45you have a further signal the DQ signal.

1:34:47>> So I think the testimony is disputed

1:34:49whether the command as a whole actually

1:34:51arrives there and I'm going to get to

1:34:53that. Um but the testimony is very clear

1:34:55and the jury didn't have to accept their

1:34:57expert testimony. The the expert's very

1:34:59clear and this is Micron's own corporate

1:35:00representative lead architect for memory

1:35:02products question. So what you're saying

1:35:04is for a DRM that's not selected its

1:35:06receiver for the command and address

1:35:08signals are disabled. So it's not

1:35:10receiving any command and address signal

1:35:12and as old it's also ignoring any of the

1:35:13data that may be coming its way. Answer

1:35:15that's right that's at 20,533.

1:35:18Same thing 25,535

1:35:20lines 19 to22. Do you know how they

1:35:23managed to ignore signals that are

1:35:24coming in? Yeah, their selects will be

1:35:26off. So the command does not flow into

1:35:28the input buffers. The evidence is very

1:35:30clear that from the view of a skilled

1:35:31artisan and Mr. Ross is a skilled

1:35:33artisan it is not received. Likewise

1:35:36micron engineer Mr. here only the device

1:35:38it says 20,564

1:35:40lines 20 to 22 only the devices which

1:35:42have DQ pulled low will accept the MRS

1:35:45command so there's ample evidence about

1:35:47received but I believe that my colleague

1:35:50didn't even address the question about

1:35:52directed to or addressed to and for

1:35:54something to be sent to or transmitted

1:35:56to you would expect it to be addressed

1:35:58to that person that it's not somebody

1:35:59who's not intended to receive it and

1:36:01micron

1:36:02>> the other side saying that your view is

1:36:05that as long as it reaches is these DRMs

1:36:08that's good enough and they do reach all

1:36:12of the DRAMs to the extent that they all

1:36:14arrive at some uh temporary buffer.

1:36:17>> So I think there's two answers. First

1:36:19reaches in a sense that an skilled

1:36:21artisan electrical engineer would

1:36:23consider relevant which is not that it's

1:36:25just on a shared bus because their

1:36:26interpretation is anything on a shared

1:36:28bus it reaches because electronically it

1:36:30passes by. That's like saying a package

1:36:31on a FedEx van reaches every house

1:36:34because the FedEx gang goes by it. What

1:36:36matters when it's received is does it

1:36:38come into and is it accepted by and if

1:36:40it's not accepted by if you tell the

1:36:42package I don't want this go away FedEx

1:36:44would not say that was transmitted to

1:36:46you and they wouldn't say it was

1:36:47delivered and they certainly wouldn't

1:36:48say it if it's not addressed to you

1:36:50don't it's not considered received

1:36:52unless it's addressed to you and

1:36:53addressing is an important part of

1:36:55transmitted to interlopers accidental

1:36:58things aren't transmitted to it's

1:36:59transmitted to the person you intend to

1:37:01send it to so if a drill sergeant looks

1:37:03at me and says lamb can drop and give me

1:37:0520 or drop and give me 20 lambkin. No

1:37:07one would say he transmitted that

1:37:09command to anybody who happened to be

1:37:11nearby and overheard it.

1:37:13>> It is addressed to all the chips. It is

1:37:15addressed to all the chips because the

1:37:17signal is sent to all the chips.

1:37:19>> No, it's only

1:37:19>> some some chips uh the selected chip can

1:37:23use it the others can't.

1:37:25>> Right. I think actually the command

1:37:26itself and maybe this is the technical

1:37:28answer but I think from this perspect we

1:37:30always look from the perspective of a

1:37:32skilled artisan and we have skilled

1:37:33artisan after skilled arson after

1:37:35skilled artisan saying it isn't received

1:37:37because it the chip gets shut off before

1:37:39received but if you want to turn to page

1:37:41I believe it's 38 of their brief which

1:37:43is the chart is

1:37:44>> received I thought we had a situation

1:37:45where was activated enabled by the DQ

1:37:50signal. Yeah, I I think I can explain

1:37:52what's happening there. If you turn to

1:37:54page 38 of their brief, and mind you,

1:37:56the jury doesn't have to accept their

1:37:58evidence. The jury could understand

1:38:00their own witness that it's not received

1:38:02by because it's shut the m the DQ0 shuts

1:38:04it down before it's actually received.

1:38:06The jury could understand that a skilled

1:38:08artisan doesn't look at questions of

1:38:10timing. For example, Dr. Mion explained

1:38:12it's all considered part of one

1:38:14transaction.

1:38:14>> Of the record is that there really isn't

1:38:16any dispute technically as to what

1:38:18happens here. It's a question of how you

1:38:20interpret it in terms of whether that is

1:38:22sufficient to have the thing.

1:38:24>> Yeah. And in so far as you have a

1:38:26question of how you interpret it. You

1:38:27the jury can take the view of a skilled

1:38:29artisan and heard from skilled artisan

1:38:30after skilled artisan that it isn't

1:38:32received. It's not received because the

1:38:34DQ0 turns it off. It's not received

1:38:36because it never flows into the input

1:38:38buffers. But even if we set that aside,

1:38:39Judge Dyke, and we want to talk about

1:38:41All right, let's talk about the timing.

1:38:42That's on page 38. And I'd like to talk

1:38:44about this because I think there's an

1:38:46inference being drawn from this that's

1:38:48not correct. If you take a look at that

1:38:50and it's correct that you start sending

1:38:53the command, right? And it starts coming

1:38:56and it's at TB, right? That's the blue

1:38:58box. It starts going at a TB and it is

1:39:01correct if you look down below to the DQ

1:39:04boxed in green. That little E which is

1:39:07your DQ0 comes out comes out a clock

1:39:11tick later. So it gets placed on a bus.

1:39:13The MRA command is placed on a bus

1:39:15slightly ahead of when or it starts

1:39:18being placed on a bus slightly ahead of

1:39:20when that EE is placed on a separate

1:39:22line, a separate asynchronous line. But

1:39:25if you look at the box and this is

1:39:26Micron's own diagram, if you take that

1:39:30box, that entire box is the signal. It's

1:39:34the command. It's not just a one or a

1:39:36zero. It's a whole string of things. So

1:39:38for the the recipient to understand what

1:39:40it's being told to do, it has to get

1:39:42that whole box. That whole box isn't

1:39:45there until TB plus 5. By the time TB+ 5

1:39:49rolls around, that little Eee has

1:39:52already arrived. And so before the full

1:39:54command gets in, before the computer

1:39:57knows, oh, this is what I'm going to be

1:39:59told to do. This is my MRS command.

1:40:01Something said, shut your door. Don't

1:40:03listen. Go to sleep. And so it never

1:40:05receives the command. And I think that I

1:40:08the the statement MRS command to DM the

1:40:10blue box that uh my colleague cites it

1:40:13says the MRS command and address inputs

1:40:15are held in the DRM. So it might be that

1:40:18some little bit gets there before the

1:40:21device before the DQ0 says shut down.

1:40:23It's not for you. Don't listen. Some bit

1:40:26a header something that causes it to

1:40:27respond in some way. But the command

1:40:29itself doesn't actually arrive because

1:40:31it's so much later than the E. and and

1:40:34and I think an analogy might be if you

1:40:36look at Morse code, so for letter J,

1:40:38it's dot dash dash dash. If the dot got

1:40:43there to the telegraph operator, but

1:40:45before he got his dash dash dash, he got

1:40:48a signal says shut down your telegraph.

1:40:50Don't receive anything else. No one

1:40:51would say the letter J dot dash dash has

1:40:54been received because only the dot made

1:40:55it. That's how this diagram is showing

1:40:58what's happening here. And so it's not

1:40:59like the evidence is un But even backing

1:41:02off from that, this court doesn't have

1:41:04to become an expert on reading diagrams.

1:41:06The jury heard evidence of how skilled

1:41:08artisans would understand this. They

1:41:10heard from Mr. Seir, a micron engineer

1:41:12that it gets will not accept it. It's

1:41:14like a package being rejected at the

1:41:16door not received. They heard from m

1:41:18They heard from um uh Mr. Ross that

1:41:21because it's shut down, the command is

1:41:23not received. That's substantial

1:41:25evidence. This court doesn't sit behind

1:41:28and say, "No, no, I'm going to read a

1:41:29diagram differently." Um, when if you

1:41:31look at the diagram, you can reconcile

1:41:33it, but you don't have to reconcile it.

1:41:34The jury was allowed to listen to their

1:41:36own witnesses and that it's not actually

1:41:38received. And certainly, you wouldn't

1:41:40think it's not it's transmitted to to

1:41:42people to whom it's not addressed. Um,

1:41:44to use one quick example, for example,

1:41:46we all use public Wi-Fi.

1:41:49Those the signals when you do an inquiry

1:41:51and it comes back, that's all being

1:41:53blasted out to the air. It actually in

1:41:55some sense reaches every device that is

1:41:58in in you know within range but it's

1:42:00addressed to only one device and only

1:42:03one device will absent some mis

1:42:06misconduct will be able to see it and

1:42:08use it and since it's directed to one

1:42:10device we would treat that as

1:42:11transmitted to spam.

1:42:13>> Pardon?

1:42:13>> You're just blasting it everywhere even

1:42:16though you really only have one true

1:42:18target

1:42:19>> right. And then if all the recipients,

1:42:23you know, are are holding it at least

1:42:26for a temporary period of time.

1:42:29>> So I think

1:42:30>> that's enough.

1:42:30>> Well, that's two two two issues. One,

1:42:32would a skilled artisan understand that

1:42:35the sign the Wi-Fi signal, the response

1:42:37to your inquiry is transmitted to people

1:42:39who basically are told to ignore it

1:42:41because it just happens to be available

1:42:43in the air to them. I don't think they'd

1:42:44understand that. But at the very least,

1:42:47Micron has to show it has the only

1:42:48reasonable understanding of the

1:42:50language. And that's not the only

1:42:52reasonable understanding the language

1:42:53because its own witnesses, its own

1:42:56witness has said, "Hey, I don't think

1:42:58it's received. I don't think it's

1:43:00received because the MR the the DQ0

1:43:03comes in time to shut it down before

1:43:05that full command is in."

1:43:06>> Where did their witness say it's not

1:43:08received?

1:43:09>> So, let's start with go through it. says

1:43:1420,533

1:43:16lines 20 to 25.

1:43:17>> Wait a moment. Which volume is this in?

1:43:19>> Um, that's going to be volume two, I

1:43:20believe.

1:43:23And this is

1:43:26Mr. Ross, who is their lead lead

1:43:28architect.

1:43:29>> What page?

1:43:30>> 20,533.

1:43:32I'll be bouncing around these few pages

1:43:33a bit.

1:43:36Lines 20 to 25.

1:43:39So what you're saying is for a DRM

1:43:41that's not selected, its receiver for

1:43:43the command and address signals are

1:43:44disabled. So it's not receiving any

1:43:46command and address signals. And as a

1:43:48result, it's also ignoring any of the

1:43:49data that may be coming its way. Answer,

1:43:51that's right. If you look two pages

1:43:54later, 20,535

1:43:56lines 1922.

1:43:58Question. Do you know how they manage to

1:44:00ignore the signals that are coming in?

1:44:02Answer: Yeah, their selects will be off.

1:44:04So the command does not flow into the

1:44:07input buffers 20,533.

1:44:10So I'm going back to the prior lines 19

1:44:12to 22

1:44:14talking about receivers on non- selected

1:44:16DRMS quote are put in a standby state if

1:44:19you will question. And in that standby

1:44:21state it ignores any signal that's on

1:44:22the data line. Is that correct? Answer

1:44:25yes or a command. So they would ignore a

1:44:27command coming in and yes if there's no

1:44:29command received then there's no data

1:44:32that's latched. Time and again he's

1:44:34making the same concession. Or if you go

1:44:35to 20,000 564 Mr. Seir who is again

1:44:40micron engineer lines 20 to 22 he says

1:44:44that only the devices that have the DQ0

1:44:46pulled low will accept the MRS command.

1:44:50Command isn't accepted if they don't

1:44:52have DQ0

1:44:54pressed low. Dr. Manion Smith. Now we're

1:44:57going to go to 20366.

1:44:59If DQ0 is not set low, the DRM chip is

1:45:03not going to receive and execute an MRS

1:45:06command. 20,367

1:45:09lines 1 to4 non- selected DRAMs quote

1:45:11will have their receivers in standby

1:45:13mode. So, they're basically asleep.

1:45:1620,512

1:45:17lines 20 to 23. And until the point in

1:45:20time when the DQ signal turns off some

1:45:22DMs and activates one, has the command

1:45:24signal been transmitted to any of the

1:45:25DMs? Answer, no. From the perspective of

1:45:28these skilled artisans, these the sig

1:45:30the DQ0 and the rest is effectively one

1:45:34transaction. Dr. Manion Smith described

1:45:37them as a single operation. So the

1:45:39address and arrive and and the signal

1:45:41itself arrive at approximately the same

1:45:43moment and it's not received because

1:45:45it's not not anything that they can

1:45:47execute on because it gets cut off

1:45:49before it can know what the command is

1:45:51consistent with that. But even so, at

1:45:53the very least, even if you don't

1:45:54require a receipt, even if you say,

1:45:56"Okay, well, you wouldn't say that it is

1:45:58transmitted to if it's not addressed to

1:46:00them." I think a skilled artist would

1:46:01understand that if it's not addressed to

1:46:03you, it's not received by. Skilled

1:46:04artisans just don't take the view that

1:46:06anything placed on the bus is

1:46:07automatically transmitted to and

1:46:09received by everything else on the bus.

1:46:11That's just not how an EE would

1:46:13understand this. And the jury certainly

1:46:15was allowed to draw that conclusion.

1:46:18If I could turn then briefly to the

1:46:20aortionment question on the 912

1:46:23and that is that that is as a matter of

1:46:26dowert as waved as wave could be because

1:46:28at the outset the only argument made at

1:46:30dowbert was there's a double count with

1:46:32the 506 but a double count isn't an

1:46:35aortionment issue. It's very different

1:46:37because

1:46:37>> what's the standard review of for us to

1:46:43consider how Judge Gilstrap understood

1:46:46the Dowbert motion because I think there

1:46:49is an alternate reading of their

1:46:51challenge which was based on more than

1:46:55the alleged double counting but that

1:46:57there was um

1:47:00an allegation by Kennedy that there were

1:47:03different technical contributions

1:47:06coming from different patents that uh

1:47:10contributed significantly and in fact

1:47:13exclusively to all of the speed benefit

1:47:16here.

1:47:16>> So actually I don't think that can be a

1:47:18con a proper construction. The judge did

1:47:20say it's a double counting issue.

1:47:22>> I guess what I'm wondering is is that a

1:47:24question of law or is that an abuse?

1:47:25It's an abuse of discretion standard

1:47:27because the judge is in the moment

1:47:29trying to figure out what the other side

1:47:30is say what they're saying to you and

1:47:32the judge if you made has a reasonable

1:47:33construction and they haven't made the

1:47:35opposite argument with clarity or at all

1:47:37there's no abuse of discretion and I

1:47:39think if I could ask the court if you

1:47:40looked at the actual motions appendix

1:47:445155 to 57 and the reply is at 5553

1:47:49these are all double counting arguments

1:47:52at no point do they say it's not

1:47:53properly

1:47:54>> was it made the argument at Dalbert.

1:47:56>> Pardon?

1:47:56>> What difference does it make whether

1:47:58they make the argument at Dalbert? They

1:48:00make the argument now based on the trial

1:48:02transcript.

1:48:03>> They're arguing based on sufficiency,

1:48:05but then you don't look and say, did the

1:48:07expert go through a set of techniques

1:48:09that we think is required? At that

1:48:11point, you're asking did the jury have

1:48:13sufficient evidence on which it could

1:48:15decide that yes, the speed benefit is

1:48:17attributable to the the technology. And

1:48:20so what

1:48:21>> it's not not a sufficiency issue.

1:48:25>> So it it becomes a sufficiency issue,

1:48:27but it's on a very different standard.

1:48:29We're not looking at technical dowert

1:48:31like was was it a reliable standard,

1:48:33reliably applied, we're going to make

1:48:34them march through the steps. It's what

1:48:36could the jury understand? And here the

1:48:38jury could understand that when Micron

1:48:41can't point to anything else that

1:48:43contributed nothing. its own expert said

1:48:46flat out that he's not able to identify

1:48:48any other contribution to it. The jury

1:48:50can understand given that there's half a

1:48:52billion dollars at stake. If there was

1:48:54something else that contributed to it,

1:48:56surely Micron would come up with that

1:48:57and that's standard fifth circuit.

1:48:59>> Was Micron barred from bringing up

1:49:01Kennedy's testimony and other litigation

1:49:04as to the

1:49:06>> contributions of the 506 patent? And so

1:49:08they couldn't say that the 506 patent

1:49:11has a has the double count because the

1:49:13double count had be eliminated. But I

1:49:15should and I see that I'm out of time.

1:49:16If I could just answer this one

1:49:17question. The key here is the 506 and

1:49:20this patent have the same benefit. They

1:49:24achieve the same result in different

1:49:26ways. And so you could have a double

1:49:28count if you demanded the same royalty

1:49:29for each. But it's not a problem of

1:49:32aortionment because it's not like one

1:49:35the benefit comes from one or the other.

1:49:36And they're not non-infringing

1:49:38alternatives to each other because both

1:49:39of them are patented. And so where you

1:49:41handle when you have two patents that

1:49:43achieve the same technical benefit,

1:49:45they'll be worth the same amount, but

1:49:46you only get to challenge claim it once.

1:49:48And so for very often in cases like

1:49:50hologic um or uh sickle, if this is

1:49:54hubane or kimar holding, what the expert

1:49:56will say is well you pay once whether

1:49:59you use one patent or the other. And so

1:50:01that's why it's not an aortionment

1:50:02problem. These two patents actually

1:50:04achieve the same benefit in different

1:50:07ways. And so you pay for that benefit,

1:50:10same amount if you use one of the

1:50:11patents or the other. So you can't sue

1:50:13them both, but you're not going to say,

1:50:14"Oh, gee, one contributed to the other."

1:50:16Nope. They're just alternative

1:50:17mechanisms for achieving the same.

1:50:18>> You get the same royalty on each patent.

1:50:20>> Pardon?

1:50:20>> You get the same royalty for each

1:50:22patent.

1:50:22>> You would have the same royalty, but

1:50:24you'd only pay it for one patent or the

1:50:26other. You wouldn't say it for both

1:50:27because that would be the double count.

1:50:28And that was what they're complaining

1:50:30about. There's no statement that oh

1:50:32we're having an aortionment. If you read

1:50:33those pages I recited. It's just nowhere

1:50:36in there suggesting that somehow that

1:50:38this was actually a problem of

1:50:41aortionment. In fact, if you look at the

1:50:42the motion to strike or the the U motion

1:50:45lemony, it's actually a 403 argument. It

1:50:47says that it's unduly prejuditial.

1:50:49Thanks so much.

1:50:49>> I think we're out of time. But I want to

1:50:51ask you the same question that Judge

1:50:53Chen asked to Mr. Rosenr. if uh

1:50:55hypothetically we were to affirm in the

1:50:57two IPRs this case is over with right

1:51:01>> so at that point we have a significant

1:51:02finius problem and yes I think at that

1:51:05point we do not have a patent anymore on

1:51:07which we can recover and so that is a

1:51:10but my my I think my best answer to that

1:51:12is don't please don't do that these are

1:51:14innovative patents and they are entitled

1:51:16to due respect thank you if there's no

1:51:18questions I see

1:51:30your honors. A few brief I'm sorry, I

1:51:32don't know how much time I have. Okay, a

1:51:36few brief points. Uh first on

1:51:40the infringement, I agree with Judge

1:51:43Dyke that there is no dispute about how

1:51:45these products work. Uh uh Mr. Lamin

1:51:49tried to come up with a dispute about

1:51:51the box on page 38. Um, I'll just say he

1:51:56offered an interpretation of the timing

1:51:58diagram. No one embraced that

1:52:01interpretation. Our uh our witness Smith

1:52:04testified to the command being held and

1:52:07stored in the device. Net list witnesses

1:52:11did not contest this. And that's at

1:52:14pages 20,859.

1:52:17And you can see it in our opening brief

1:52:19more fully at pages 38 to 39. Now, I'm

1:52:23not saying that every uh everything on a

1:52:26bus is received because the bus passes

1:52:29by. I'm saying everything on a bus is

1:52:31received because it's received. It goes

1:52:34directly into each device. Our witnesses

1:52:38did not dispute how the devices work.

1:52:42They are offering that is my friend is

1:52:44offering Ross and Seir. All they are

1:52:47talking about in all of that testimony

1:52:50is what happens when the DQ0 signal

1:52:53comes in, which is way too late for us

1:52:56to be talking about whether it was

1:52:58received or not. Um the uh and and you

1:53:02can see it in particular when it comes

1:53:05to Ross's um testimony.

1:53:10Um Ross says that a non- selective

1:53:13device will not quote act on the signals

1:53:16of the command sent to it. That's at 533

1:53:19to 35 20,000 that is 533 to 35. He says

1:53:24the data does not latch in. That's all

1:53:26about what happens inside the device.

1:53:29Even the quote about received that my

1:53:31friend points you to Ross was not

1:53:34talking about when the command signal

1:53:36arrives. He's talking about something

1:53:38that comes way later when it's already

1:53:40inside. Um, uh, Judge Dyke, you you said

1:53:44it exactly right about addressed. We

1:53:46know that it is addressed to each device

1:53:50on the rank because it goes directly to

1:53:53each device on the rank and no one

1:53:55disputed that. And finally, we fully

1:53:59reserved our aortionment argument. Um,

1:54:02my friend on the other side talks about

1:54:04our Dowert motion. It's fully uh uh

1:54:08preserved in our Dowart motion. But if

1:54:11you look in particular at our reply, um

1:54:16uh we we said it at 5155,

1:54:20what Kennedy ar what we argued was that

1:54:22Kennedy quote does not reliably aortion

1:54:25the value of the asserted P uh patents.

1:54:29Our Dow reply is at 5554

1:54:32to 55. You can see that again it must be

1:54:36aortioned out. It doesn't matter whether

1:54:38there was double counting or not. The

1:54:41reply was after the 506 patent was

1:54:44already out of the case. And then the

1:54:47the to punctuate it 259 to 61. We say it

1:54:51four times in oral argument. quote,

1:54:54"Even if the opportunity to recover for

1:54:57the 506 patent went away when they

1:54:59dropped when they dropped it, the quote

1:55:02increase in speed attributable to the

1:55:04506 patent either has to be aortioned to

1:55:07the other patent or it has to be

1:55:10aortioned to the public where Netlist

1:55:12can't recover."

1:55:14>> Okay, I think we're out of time.

1:55:15>> Thank you, your honors. For all of these

1:55:16reasons, we respectfully request that

1:55:19the court reverse. Thank you. Thank both

1:55:22council cases submitted.

1:55:24That leads to our final case this

1:55:26morning which is number 25202

1:55:30Bergen versus Collins.

1:56:39Okay, Mr. Deacquest.

1:56:50May I please the court Kennedy the

1:56:51Hawkins for Mr. Bergen. Um on behalf of

1:56:54Mr. Bergen, I want to thank the

1:56:55opportunity this court for the

1:56:56opportunity to present his appeal.

1:56:58Veterans lack the ability to show that

1:57:00they did not receive a mailing outside

1:57:03of showing there was a problem with that

1:57:05mailing.

1:57:06Henderson recognizes that a different

1:57:08approach is needed for veterans,

1:57:09particularly when an appeal to the court

1:57:11is involved. If there's a defect in the

1:57:13mailing

1:57:15that explains why the mailing never

1:57:17arrived,

1:57:20then that explains why the the mailing

1:57:22never arrived. But if there is no defect

1:57:24in the mailing, then the veteran must

1:57:26still be able to to convince the court

1:57:28that he or his attorney did not receive

1:57:31that mailing. Mr. Bergen asked his court

1:57:34to consider whether it was error for the

1:57:36veterans court to rely upon the

1:57:38presumption of regularity to find that a

1:57:40mailed notice of a decision reached his

1:57:43attorney. He asked his court to hold

1:57:45that although the presumption should be

1:57:46used to presume that VA mailed the

1:57:48notice letter, it is improper to use

1:57:50this presumption to also presume that

1:57:53his attorney received the notice.

1:57:56He asked the court to set aside the

1:57:57veterans court order dismissing the

1:57:59appeal and remand the matter to

1:58:01determine whether his attorney received

1:58:03the notice letter.

1:58:04>> But isn't it correct that um 7266A

1:58:09at the time

1:58:11um set the standard as to when the

1:58:15notice is mailed, not when it's

1:58:17received.

1:58:19>> It it does, your honor. And um but the

1:58:22problem with with the problem that this

1:58:24case demonstrates is assuming as the you

1:58:28know the court found that there was no

1:58:30defect in the mailing despite our best

1:58:31efforts to convince them otherwise. So

1:58:33assuming that there can be there is no

1:58:35defect the VA did everything it was

1:58:37supposed to do. For some reason it never

1:58:40showed up in his attorney's mailbox.

1:58:44Under the current case law, the

1:58:46presumption of regularity has now

1:58:48extended beyond what the ve the VA did,

1:58:50beyond what the agency has done and

1:58:52presumes that it arrived where it was

1:58:54supposed to. And when as here the

1:58:58attorney uh or the veteran in other

1:59:00cases um did not receive that, the the

1:59:04presumption of regularity then becomes

1:59:06an impenetrable barrier to showing that

1:59:09there was no notice. And without the the

1:59:11notice of the decision, the veteran or

1:59:14the attorney cannot know or be put on

1:59:17notice that anything had happened with

1:59:18their claim. And so it would be it would

1:59:21be um

1:59:24it would it would not be um right to

1:59:27require them to still um abide by the

1:59:30120day deadline to file the appeal. Now,

1:59:33in this case, as soon as the attorney

1:59:35became aware of the decision, he

1:59:38immediately filed his appeal. And of

1:59:39course um it was much too it was much

1:59:42later than the 1820 days contemplated by

1:59:45the statute. But to answer the question,

1:59:47yes, the statute does

1:59:50um does start the clock from when the

1:59:53decision is mailed. But the current

1:59:55>> that's that's the standard. Well, that

1:59:57is your honor, except that when the

2:00:00notice isn't isn't uh received by the

2:00:04veteran, he or she has no idea or the

2:00:08attorney uh no idea that a decision has

2:00:10been made. And so there has to be a rule

2:00:13particularly in light of Henderson where

2:00:15the court um where the court talked

2:00:19about the solicitude of uh the V VR VGA

2:00:23and the subsequent laws that place a

2:00:25thumb on the scale in the veterans

2:00:27favor. And we believe that the the

2:00:30ruling in Henderson requires a

2:00:32re-examination of the traditional role

2:00:35of the presumption of regularity in

2:00:37veterans benefit cases. um particularly

2:00:40in uh its role in assuming as the court

2:00:43did here that the the mailing actually

2:00:46went to and was received by the veteran

2:00:48or in this case his attorney. Um

2:00:53>> well Hendendrickson talks about the

2:00:54consequences of a mailing and open the

2:00:58door to equitable tolling but that

2:01:02didn't change what triggers the timing

2:01:07in the first place. And in this case at

2:01:10the time the statute triggered that to

2:01:14the date of mailing

2:01:16>> it. Yes, your honor. And and granted

2:01:19that is a a a difficult burden to

2:01:21overcome uh or obstacle to overcome. But

2:01:24again, we think that there there there

2:01:27has to be a rule in place in order to

2:01:29allow a veteran to show and demonstrate

2:01:31that he or she did not receive the

2:01:34mailing despite the presumption of

2:01:36regularity. How does that become

2:01:38relevant? Is that relevant to equitable

2:01:39tolling? What

2:01:42>> how do you fit that into the statuto

2:01:43scheme?

2:01:44>> So, as Henderson uh confirms the the

2:01:48120day deadline is a claims processing

2:01:50rule and the court under 7266 or the VA

2:01:54under their own rules, uh claims

2:01:56processing rules can uh provide

2:01:58equitable relief in whatever form that

2:02:01they they desire uh whether it's

2:02:03equitable tolling or something else.

2:02:05What I'm asking you, how does nonreceipt

2:02:07fit into this? Is that a ground for

2:02:09equitable tolling? Is that what you're

2:02:11saying?

2:02:11>> Um, I believe it can be. Yes, your

2:02:13honor. And so when the the the receipt

2:02:17is not established or the veteran can

2:02:20show that it was never given and and

2:02:22keep in mind that the veterans court

2:02:23didn't get there and so we don't know

2:02:25what the what what evidence is needed to

2:02:27make this showing. Uh whether the

2:02:30evidence that that Mr. Bert. Um,

2:02:32>> why wouldn't it just be the standard for

2:02:33equitable tolling? You know, I I didn't

2:02:37meet the statutory deadline, but here's

2:02:40the reason. I have uh really good

2:02:42grounds because I actually never

2:02:44received the mailing uh from from the

2:02:48post office.

2:02:49>> The problem is, your honor, and and we

2:02:52think that that would be a good rule

2:02:54except that the Veterans Court with this

2:02:56ruling used the presumption of

2:02:58regularity to find that Mr. Bergen did

2:03:01or his attorney did actually receive the

2:03:04notice and that's where

2:03:05>> would have the opportunity to overcome

2:03:08the presumption of regularity.

2:03:12>> Well, we think

2:03:13>> and support the argument that you know

2:03:17equitable tolling should apply because I

2:03:19never received this notice. Um, yes,

2:03:23your honor, except again the the the

2:03:25court used the presumption of regularity

2:03:27to show that he did receive it. And the

2:03:30standard for overcoming the presumption

2:03:32of regularity is to demonstrate a defect

2:03:35in the mailing process or some defect in

2:03:38the process that the agency used.

2:03:40>> To the extent that you're arguing that

2:03:41there's no presumption of regularity

2:03:43about the mailing, I think you lose. I I

2:03:45don't I don't think you've got an

2:03:46argument.

2:03:47>> No, your honor. And and to the extent

2:03:48our briefing says that, we we disavow

2:03:50that. That is not at all what what our

2:03:52position is here.