Full transcript
0:01With this video, we will step through
0:03executing a program on our hypothetical
0:06microprocessor.
0:08Uh you see in the dotted box in figure
0:112-12 the essential components and
0:13registers within uh the hypothetical
0:17microprocessor that we've covered so
0:19far. And also you see the memory block
0:24below with addresses on the left, binary
0:28contents of those addresses in the
0:30center column and then the pneummonics
0:32or content decimal contents uh that
0:36those binary uh bit patterns represent.
0:39And so as we have discussed previously
0:44the computer or microprocessor goes
0:46through a fetch execute cycle. The first
0:49thing we're going to look at here is the
0:52fetch phase. And so with the fetch
0:55phase, we are taking the program that is
0:58in the memory block down here. We're
1:01going to execute that program beginning
1:03at address zero. It is going to go out
1:08and when you start running the program
1:09from that originating address, it's
1:12going to go to address zero. You see up
1:14here the address zero from the program
1:17counter is being transferred to the
1:19address register. Okay. Then it's going
1:22to go to that address in memory and it's
1:25going to uh read the contents of address
1:28zero, place that on the data bus, stick
1:32it in the data register. Since we're in
1:34the fetch phase, it's going to go to the
1:36instruction decoder. And so we'll kind
1:39of see that happen play by play. When
1:41the address zero is transferred to from
1:45the program counter to the address
1:47register, notice that the program
1:49counter is automatically incremented or
1:52one added to it. So that it's now ready
1:56for the successive address after the
1:59very first one.
2:02As we scroll down, we see address zero
2:04is placed on the address bus that points
2:07to and is decoded by the address
2:10decoder. and unlocks or selects uh
2:14address zero in the memory block. This
2:16is going to be a read operation.
2:19Okay. Uh because we're in the fetch
2:21cycle and we need to go out and and get
2:23an instruction.
2:27The contents the hex 86 which is the
2:32load accumulator instruction.
2:35uh that hex that uh binary content is
2:38placed on the address bus and then it is
2:41then latched into the data register. I
2:44said address bus the data bus and once
2:46it goes from the data bus then it is
2:48latched into the data register and so
2:51there is the contents hex 8 1 0 0 and
2:55then 6 0 1 1 0 that gets latched into
2:59the data register. So now it's been
3:00retrieved from memory and it's on board
3:03in the processor. Remember, we're still
3:06in the fetch phase. The hex 86 or hex86
3:10is the op code and uh it is an
3:13instruction, first instruction in the uh
3:16program. Since we're in the fetch phase,
3:18it's automatically taken from the D data
3:21register to the instruction decoder and
3:24that bit pattern is identified in a
3:27lookup table called a mapping ROM as an
3:30LDA or load accumulator instruction that
3:34gives the list of uh uh control
3:38sequences that on the control bus that
3:41need to take place in order to load the
3:45accumulator with the contents of the
3:47next address in memory. That's called a
3:50load immediate. The immediately
3:53following address in memory has the
3:56contents that's going to end up being
3:58loaded into the accumulator. So right
4:01now we have completed the fetch phase of
4:06uh this fetch execute cycle in the very
4:08with the very first instruction. Uh the
4:11op code has been decoded and it's
4:13identified as the LDA instruction. Now
4:16it's time for the processor to carry out
4:18and execute that instruction.
4:21So we enter the execute phase of the
4:24instruction. Remember the contents of
4:26the program counter were automatically
4:29incremented from 0 to one. That's being
4:31placed in the address register and it's
4:34going to be incremented from 1 to two.
4:36The program counter is uh the address
4:39register will take the address one.
4:41It'll place it on the address bus. uh
4:44that'll uh be decoded and looked up in
4:48the memory block in address one and the
4:52contents of that which is the op the
4:55operand the data uh uh the contents of
4:5907
5:00will then be read out of the next memory
5:04location after the LDA instruction and
5:07it will be placed on the uh data bus
5:10that'll be latched into the data
5:12register. But here the controller
5:14sequencer still executing that load
5:16accumulator instruction is going to take
5:18the contents of the data register and
5:21place it in the accumulator. That
5:23completes the process of the first
5:26entire instruction. If I say the entire
5:28instruction is the op code plus the
5:31operand uh and all of the processes that
5:35are associated with that load
5:37accumulator instruction. Now all of that
5:39is complete and so uh this would be a
5:42two byte instruction and that
5:45instruction requires both the op code
5:48the LDA instruction hex 86 and it
5:52requires the operand uh in the next uh
5:56uh immediately following next memory
5:59location. It's a load immediate
6:00instruction. So it takes that next
6:02memory location contents 07 and takes it
6:06from the data bus to the data register
6:09to the accumulator and latches it into
6:12the accumulator. So that instruction is
6:15now complete. It's been fetched,
6:17decoded, executed, and now the fetch
6:21execute cycle can do nothing but start
6:23over with another fetch. And so
6:26whatever's next uh and we know what's
6:29next because we look in the or where we
6:31know where the next location uh to be
6:35fetched is because the program counter
6:37was automatically incremented from 1 to
6:39two. And now address number two which is
6:42actually the third address. Remember we
6:44started at zero. So 0 one two. The third
6:48address is going to be the next address
6:50to be u read and taken to the data
6:55register and then to the instruction
6:57decoder and will be decoded as the next
7:00instruction. We'll see that happen here.
7:03Uh two is transferred from the program
7:05counter to the address register.
7:06Remember the program counter will
7:08successfively be uh incremented after
7:10that transfer is complete. Two is placed
7:12on the address bus. Uh address 2 is
7:15decoded. The contents of address 2 is
7:18placed on the data bus. Uh that is the
7:21uh what is that 8B the ad instruction
7:24placed on the data bus latched into the
7:26data register taken to the instruction
7:28decoder and decoded as the ad
7:31instruction. Fetch phase is complete.
7:34Then we're going to take care of adding
7:36immediately which immediately means the
7:39next immediate address which will be
7:41address number three. The fourth address
7:44in the list um will be the operand to be
7:48added to the contents of the accumulator
7:51which we previously loaded as seven.
7:56So here's what that looks like. Uh here
8:00is the program counter with three in it.
8:03Uh transfers the address register down
8:05address three. The fourth address in the
8:08list uh has the operand of 10 in it. uh
8:13and see you uh the the it' be 0a would
8:17be the hex contents of memory right
8:19there and then that is transferred to
8:22the data bus and the data register and
8:24it goes to the other input of the alu.
8:28So uh then the execute we're in the
8:31middle of the execution of the immediate
8:33ad. Uh the seven and the 10 are added
8:37together to give us 17. Okay, that's
8:41talking in decimal terms. Uh that sum
8:44value is then uh taken from the alou and
8:48it overwrites the previous contents of
8:50the accumulator which was seven. It
8:53overwrites it with that 17. So you see
8:56the the contents in there 00001 00001
9:01um that would be a one one in hexadimal
9:05but if you look at it from our sum of
9:07weights method uh we got a one in the
9:10onees place and then we have the twos
9:12fours 8s the 16's place has a one so 16
9:17+ one that's the only two weights that
9:19have a one with them 16 + 1 is 17 so
9:23there u it is it is uh done. We we've
9:26completed the execution phase of the add
9:30immediate instruction and now fetch
9:32execute is going to start over. We're
9:34going to go back to the next successive
9:37memory location which is going to be
9:39memory location 4. Uh this figure
9:41doesn't show that incremented just yet,
9:44but it will it would have been
9:45incremented just as soon as that
9:47transfer was made. And we'll have a four
9:50there. And here you see it in this
9:52picture. They've got the four in the
9:53program counter. Transfers to the
9:55address register to the address bus.
9:58Goes down to address 4. Finds the hex 3E
10:02halt instruction. Takes it to the data
10:05bus. Then to the data register, then to
10:07the instruction decoder, looked up in
10:09the mapping ROM, found to be the halt
10:11instruction, and for all intents and
10:14purposes at this point in our journey,
10:17uh that halt instruction simply stops
10:20the fetch execute cycle. So everything
10:22is frozen with our trainer or emulator.
10:26We can hit the reset instruction or the
10:29reset button uh on the the keypad at
10:32this point and we'll get CPU up. We'll
10:34come up on the seven segment displays
10:36and then we can go look at the
10:38accumulator by hitting the accumulate
10:40acca button and the accumulator button
10:43will show us the one one hex which we
10:47know up here is our sum of 17.
10:54You've got a self test to take care of
10:55here and then the answers are provided
10:58after that. So test yourself. Uh you can
11:01read through that again kind of play by
11:03play. I just kind of wanted to give you
11:06my u summation of that and maybe that uh
11:10kind of faster explanation helps you
11:12follow through uh without getting lost
11:14in those steps. But just remember the
11:17fetch execute cycle happens over and
11:19over and over again until it's stopped
11:20by a halt instruction. The very first
11:22thing it does it fetches it takes that
11:25to the instruction decoder to find out
11:27what instruction what to do and then it
11:29carries out or executes that instruction
11:32and then the fetch execute cycle starts
11:34all over again. That's the main point of
11:36this section in the book and hopefully
11:39you're starting to get that mental model
11:41of the hypothetical microprocessor.
11:44you're starting to learn learn how the
11:46different registers and counters and
11:48components of the microprocessor
11:50interact with each other and get in sort
11:53of a lockstep routine of how this
11:55machine works. You know, it it could
11:58have uh gears and pulleys and belts and
12:00chains and that kind of thing and be a
12:02mechanical machine. It is an electronic
12:05microprocessor machine or electronic
12:07digital type machine instead, but it
12:10still has a lock step very mechanical uh
12:14feel to it and a and a and a very
12:16logical operation to it. We're we're
12:19getting into the sandbox and we're
12:21realizing this thing is not magic that
12:23it does nothing but follow our
12:26instructions. It's just that it can do
12:28it very fast and the instructions can be
12:30very complex and that makes it uh uh
12:34very powerful to use.